Re: [PATCH 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id

[Igor Mammedov]

On Mon, 18 Oct 2021 23:38:26 +0800
Bin Meng <bmeng.cn@gmail.com> wrote:

> Using memory_region_init_ram(), which can't possibly handle vhost-user,
> and can't work as expected with '-numa node,memdev' options.
> 
> Use MachineState::ram instead of manually initializing RAM memory
> region, as well as by providing MachineClass::default_ram_id to
> opt in to memdev scheme.
> 
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Igor Mammedov <imammedo@redhat.com>

> ---
> 
>  hw/riscv/shakti_c.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
> index d7d1f91fa5..90e2cf609f 100644
> --- a/hw/riscv/shakti_c.c
> +++ b/hw/riscv/shakti_c.c
> @@ -45,7 +45,6 @@ static void shakti_c_machine_state_init(MachineState 
> *mstate)
>  {
>      ShaktiCMachineState *sms = RISCV_SHAKTI_MACHINE(mstate);
>      MemoryRegion *system_memory = get_system_memory();
> -    MemoryRegion *main_mem = g_new(MemoryRegion, 1);
>  
>      /* Allow only Shakti C CPU for this platform */
>      if (strcmp(mstate->cpu_type, TYPE_RISCV_CPU_SHAKTI_C) != 0) {
> @@ -59,11 +58,9 @@ static void shakti_c_machine_state_init(MachineState 
> *mstate)
>      qdev_realize(DEVICE(&sms->soc), NULL, &error_abort);
>  
>      /* register RAM */
> -    memory_region_init_ram(main_mem, NULL, "riscv.shakti.c.ram",
> -                           mstate->ram_size, &error_fatal);
>      memory_region_add_subregion(system_memory,
>                                  shakti_c_memmap[SHAKTI_C_RAM].base,
> -                                main_mem);
> +                                mstate->ram);
>  
>      /* ROM reset vector */
>      riscv_setup_rom_reset_vec(mstate, &sms->soc.cpus,
> @@ -88,6 +85,7 @@ static void shakti_c_machine_class_init(ObjectClass *klass, 
> void *data)
>      mc->desc = "RISC-V Board compatible with Shakti SDK";
>      mc->init = shakti_c_machine_state_init;
>      mc->default_cpu_type = TYPE_RISCV_CPU_SHAKTI_C;
> +    mc->default_ram_id = "riscv.shakti.c.ram";
>  }
>  
>  static const TypeInfo shakti_c_machine_type_info = {