[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineCl
From: |
Bin Meng |
Subject: |
Re: [PATCH 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id |
Date: |
Tue, 19 Oct 2021 20:57:28 +0800 |
Hi Igor,
On Tue, Oct 19, 2021 at 3:11 PM Igor Mammedov <imammedo@redhat.com> wrote:
>
> On Mon, 18 Oct 2021 23:38:25 +0800
> Bin Meng <bmeng.cn@gmail.com> wrote:
>
> > Using memory_region_init_ram(), which can't possibly handle vhost-user,
> > and can't work as expected with '-numa node,memdev' options.
> >
> > Use MachineState::ram instead of manually initializing RAM memory
> > region, as well as by providing MachineClass::default_ram_id to
> > opt in to memdev scheme.
> >
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >
> > hw/riscv/opentitan.c | 6 ++----
> > 1 file changed, 2 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> > index 9803ae6d70..c356293d29 100644
> > --- a/hw/riscv/opentitan.c
> > +++ b/hw/riscv/opentitan.c
> > @@ -67,17 +67,14 @@ static void opentitan_board_init(MachineState *machine)
> > const MemMapEntry *memmap = ibex_memmap;
> > OpenTitanState *s = g_new0(OpenTitanState, 1);
> > MemoryRegion *sys_mem = get_system_memory();
> > - MemoryRegion *main_mem = g_new(MemoryRegion, 1);
>
> It is likely that you are missing fixed size check here
> (looking at code it seems to me that board doesn't support variable RAM size)
> See commit 00b9829f83c for example.
Yep
>
> > /* Initialize SoC */
> > object_initialize_child(OBJECT(machine), "soc", &s->soc,
> > TYPE_RISCV_IBEX_SOC);
> > qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
> >
> > - memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
> > - memmap[IBEX_DEV_RAM].size, &error_fatal);
> > memory_region_add_subregion(sys_mem,
> > - memmap[IBEX_DEV_RAM].base, main_mem);
> > + memmap[IBEX_DEV_RAM].base, machine->ram);
> >
> > if (machine->firmware) {
> > riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base,
> > NULL);
> > @@ -95,6 +92,7 @@ static void opentitan_machine_init(MachineClass *mc)
> > mc->init = opentitan_board_init;
> > mc->max_cpus = 1;
> > mc->default_cpu_type = TYPE_RISCV_CPU_IBEX;
> > + mc->default_ram_id = "riscv.lowrisc.ibex.ram";
>
> Are you missing "mc->default_ram_size = memmap[IBEX_DEV_RAM].size" here?
Indeed, thanks for the review!
>
> otherwise it will default to generic:
> hw/core/machine.c: mc->default_ram_size = 128 * MiB;
>
> > }
> >
> > DEFINE_MACHINE("opentitan", opentitan_machine_init)
>
Regards,
Bin
- [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 2/6] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 3/6] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 4/6] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 5/6] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- [PATCH 6/6] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id, Bin Meng, 2021/10/18
- Re: [PATCH 1/6] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id, Philippe Mathieu-Daudé, 2021/10/18