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[PULL 15/33] target/riscv: Replace is_32bit with get_xl/get_xlen
From: |
Alistair Francis |
Subject: |
[PULL 15/33] target/riscv: Replace is_32bit with get_xl/get_xlen |
Date: |
Fri, 22 Oct 2021 23:37:54 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
In preparation for RV128, replace a simple predicate
with a more versatile test.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-9-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 77cad9bc45..d0ba54091e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -91,15 +91,18 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
}
#ifdef TARGET_RISCV32
-# define is_32bit(ctx) true
+#define get_xl(ctx) MXL_RV32
#elif defined(CONFIG_USER_ONLY)
-# define is_32bit(ctx) false
+#define get_xl(ctx) MXL_RV64
#else
-static inline bool is_32bit(DisasContext *ctx)
+#define get_xl(ctx) ((ctx)->xl)
+#endif
+
+/* The word size for this machine mode. */
+static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
{
- return ctx->xl == MXL_RV32;
+ return 16 << get_xl(ctx);
}
-#endif
/* The word size for this operation. */
static inline int oper_len(DisasContext *ctx)
@@ -257,7 +260,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong
imm)
static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
- target_ulong sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+ target_ulong sd = get_xl(ctx) == MXL_RV32 ? MSTATUS32_SD : MSTATUS64_SD;
if (ctx->mstatus_fs != MSTATUS_FS) {
/* Remember the state change for the rest of the TB. */
@@ -316,16 +319,16 @@ EX_SH(12)
} \
} while (0)
-#define REQUIRE_32BIT(ctx) do { \
- if (!is_32bit(ctx)) { \
- return false; \
- } \
+#define REQUIRE_32BIT(ctx) do { \
+ if (get_xl(ctx) != MXL_RV32) { \
+ return false; \
+ } \
} while (0)
-#define REQUIRE_64BIT(ctx) do { \
- if (is_32bit(ctx)) { \
- return false; \
- } \
+#define REQUIRE_64BIT(ctx) do { \
+ if (get_xl(ctx) < MXL_RV64) { \
+ return false; \
+ } \
} while (0)
static int ex_rvc_register(DisasContext *ctx, int reg)
--
2.31.1
- [PULL 05/33] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh, (continued)
- [PULL 05/33] target/riscv: fix TB_FLAGS bits overlapping bug for rvv/rvh, Alistair Francis, 2021/10/22
- [PULL 06/33] target/riscv: Remove some unused macros, Alistair Francis, 2021/10/22
- [PULL 07/33] target/riscv: Organise the CPU properties, Alistair Francis, 2021/10/22
- [PULL 08/33] target/riscv: Move cpu_get_tb_cpu_state out of line, Alistair Francis, 2021/10/22
- [PULL 09/33] target/riscv: Create RISCVMXL enumeration, Alistair Francis, 2021/10/22
- [PULL 10/33] target/riscv: Split misa.mxl and misa.ext, Alistair Francis, 2021/10/22
- [PULL 12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Alistair Francis, 2021/10/22
- [PULL 11/33] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Alistair Francis, 2021/10/22
- [PULL 13/33] target/riscv: Use REQUIRE_64BIT in amo_check64, Alistair Francis, 2021/10/22
- [PULL 14/33] target/riscv: Properly check SEW in amo_op, Alistair Francis, 2021/10/22
- [PULL 15/33] target/riscv: Replace is_32bit with get_xl/get_xlen,
Alistair Francis <=
- [PULL 16/33] target/riscv: Replace DisasContext.w with DisasContext.ol, Alistair Francis, 2021/10/22
- [PULL 17/33] target/riscv: Use gen_arith_per_ol for RVM, Alistair Francis, 2021/10/22
- [PULL 18/33] target/riscv: Adjust trans_rev8_32 for riscv64, Alistair Francis, 2021/10/22
- [PULL 19/33] target/riscv: Use gen_unary_per_ol for RVB, Alistair Francis, 2021/10/22
- [PULL 20/33] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Alistair Francis, 2021/10/22
- [PULL 22/33] target/riscv: Compute mstatus.sd on demand, Alistair Francis, 2021/10/22
- [PULL 21/33] target/riscv: Use riscv_csrrw_debug for cpu_dump, Alistair Francis, 2021/10/22
- [PULL 23/33] hw/riscv: opentitan: Update to the latest build, Alistair Francis, 2021/10/22
- [PULL 25/33] hw/intc: sifive_plic: Move the properties, Alistair Francis, 2021/10/22
- [PULL 26/33] hw/intc: sifive_plic: Cleanup the realize function, Alistair Francis, 2021/10/22