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[PULL 19/33] target/riscv: Use gen_unary_per_ol for RVB
From: |
Alistair Francis |
Subject: |
[PULL 19/33] target/riscv: Use gen_unary_per_ol for RVB |
Date: |
Fri, 22 Oct 2021 23:37:58 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
The count zeros instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-13-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 16 ++++++++++++
target/riscv/insn_trans/trans_rvb.c.inc | 33 ++++++++++++-------------
2 files changed, 32 insertions(+), 17 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index cb515e2a3c..f3a5870ad0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -486,6 +486,22 @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a,
DisasExtend ext,
return true;
}
+static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+ void (*f_tl)(TCGv, TCGv),
+ void (*f_32)(TCGv, TCGv))
+{
+ int olen = get_olen(ctx);
+
+ if (olen != TARGET_LONG_BITS) {
+ if (olen == 32) {
+ f_tl = f_32;
+ } else {
+ g_assert_not_reached();
+ }
+ }
+ return gen_unary(ctx, a, ext, f_tl);
+}
+
static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index d6f9e9fc83..4eb41756fa 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -47,10 +47,18 @@ static void gen_clz(TCGv ret, TCGv arg1)
tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
}
+static void gen_clzw(TCGv ret, TCGv arg1)
+{
+ TCGv t = tcg_temp_new();
+ tcg_gen_shli_tl(t, arg1, 32);
+ tcg_gen_clzi_tl(ret, t, 32);
+ tcg_temp_free(t);
+}
+
static bool trans_clz(DisasContext *ctx, arg_clz *a)
{
REQUIRE_ZBB(ctx);
- return gen_unary(ctx, a, EXT_ZERO, gen_clz);
+ return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
}
static void gen_ctz(TCGv ret, TCGv arg1)
@@ -58,10 +66,15 @@ static void gen_ctz(TCGv ret, TCGv arg1)
tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
}
+static void gen_ctzw(TCGv ret, TCGv arg1)
+{
+ tcg_gen_ctzi_tl(ret, arg1, 32);
+}
+
static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
{
REQUIRE_ZBB(ctx);
- return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
+ return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw);
}
static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
@@ -317,14 +330,6 @@ static bool trans_zext_h_64(DisasContext *ctx,
arg_zext_h_64 *a)
return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
}
-static void gen_clzw(TCGv ret, TCGv arg1)
-{
- TCGv t = tcg_temp_new();
- tcg_gen_shli_tl(t, arg1, 32);
- tcg_gen_clzi_tl(ret, t, 32);
- tcg_temp_free(t);
-}
-
static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
{
REQUIRE_64BIT(ctx);
@@ -332,17 +337,11 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
return gen_unary(ctx, a, EXT_NONE, gen_clzw);
}
-static void gen_ctzw(TCGv ret, TCGv arg1)
-{
- tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
- tcg_gen_ctzi_tl(ret, ret, 64);
-}
-
static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
{
REQUIRE_64BIT(ctx);
REQUIRE_ZBB(ctx);
- return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
+ return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
}
static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
--
2.31.1
- [PULL 09/33] target/riscv: Create RISCVMXL enumeration, (continued)
- [PULL 09/33] target/riscv: Create RISCVMXL enumeration, Alistair Francis, 2021/10/22
- [PULL 10/33] target/riscv: Split misa.mxl and misa.ext, Alistair Francis, 2021/10/22
- [PULL 12/33] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Alistair Francis, 2021/10/22
- [PULL 11/33] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Alistair Francis, 2021/10/22
- [PULL 13/33] target/riscv: Use REQUIRE_64BIT in amo_check64, Alistair Francis, 2021/10/22
- [PULL 14/33] target/riscv: Properly check SEW in amo_op, Alistair Francis, 2021/10/22
- [PULL 15/33] target/riscv: Replace is_32bit with get_xl/get_xlen, Alistair Francis, 2021/10/22
- [PULL 16/33] target/riscv: Replace DisasContext.w with DisasContext.ol, Alistair Francis, 2021/10/22
- [PULL 17/33] target/riscv: Use gen_arith_per_ol for RVM, Alistair Francis, 2021/10/22
- [PULL 18/33] target/riscv: Adjust trans_rev8_32 for riscv64, Alistair Francis, 2021/10/22
- [PULL 19/33] target/riscv: Use gen_unary_per_ol for RVB,
Alistair Francis <=
- [PULL 20/33] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Alistair Francis, 2021/10/22
- [PULL 22/33] target/riscv: Compute mstatus.sd on demand, Alistair Francis, 2021/10/22
- [PULL 21/33] target/riscv: Use riscv_csrrw_debug for cpu_dump, Alistair Francis, 2021/10/22
- [PULL 23/33] hw/riscv: opentitan: Update to the latest build, Alistair Francis, 2021/10/22
- [PULL 25/33] hw/intc: sifive_plic: Move the properties, Alistair Francis, 2021/10/22
- [PULL 26/33] hw/intc: sifive_plic: Cleanup the realize function, Alistair Francis, 2021/10/22
- [PULL 30/33] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id, Alistair Francis, 2021/10/22
- [PULL 29/33] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id, Alistair Francis, 2021/10/22
- [PULL 27/33] hw/intc: sifive_plic: Cleanup the irq_request function, Alistair Francis, 2021/10/22
- [PULL 28/33] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id, Alistair Francis, 2021/10/22