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[PULL 27/33] hw/intc: sifive_plic: Cleanup the irq_request function
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From: |
Alistair Francis |
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Subject: |
[PULL 27/33] hw/intc: sifive_plic: Cleanup the irq_request function |
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Date: |
Fri, 22 Oct 2021 23:38:06 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id:
4200da222a65c89ed1ba35f754dcca7fdd9f08d6.1634524691.git.alistair.francis@wdc.com
---
hw/intc/sifive_plic.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index d77a5ced23..877e76877c 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -412,12 +412,10 @@ static void parse_hart_config(SiFivePLICState *plic)
static void sifive_plic_irq_request(void *opaque, int irq, int level)
{
- SiFivePLICState *plic = opaque;
- if (RISCV_DEBUG_PLIC) {
- qemu_log("sifive_plic_irq_request: irq=%d level=%d\n", irq, level);
- }
- sifive_plic_set_pending(plic, irq, level > 0);
- sifive_plic_update(plic);
+ SiFivePLICState *s = opaque;
+
+ sifive_plic_set_pending(s, irq, level > 0);
+ sifive_plic_update(s);
}
static void sifive_plic_realize(DeviceState *dev, Error **errp)
--
2.31.1
- [PULL 18/33] target/riscv: Adjust trans_rev8_32 for riscv64, (continued)
- [PULL 18/33] target/riscv: Adjust trans_rev8_32 for riscv64, Alistair Francis, 2021/10/22
- [PULL 19/33] target/riscv: Use gen_unary_per_ol for RVB, Alistair Francis, 2021/10/22
- [PULL 20/33] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Alistair Francis, 2021/10/22
- [PULL 22/33] target/riscv: Compute mstatus.sd on demand, Alistair Francis, 2021/10/22
- [PULL 21/33] target/riscv: Use riscv_csrrw_debug for cpu_dump, Alistair Francis, 2021/10/22
- [PULL 23/33] hw/riscv: opentitan: Update to the latest build, Alistair Francis, 2021/10/22
- [PULL 25/33] hw/intc: sifive_plic: Move the properties, Alistair Francis, 2021/10/22
- [PULL 26/33] hw/intc: sifive_plic: Cleanup the realize function, Alistair Francis, 2021/10/22
- [PULL 30/33] hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id, Alistair Francis, 2021/10/22
- [PULL 29/33] hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id, Alistair Francis, 2021/10/22
- [PULL 27/33] hw/intc: sifive_plic: Cleanup the irq_request function,
Alistair Francis <=
- [PULL 28/33] hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id, Alistair Francis, 2021/10/22
- [PULL 31/33] hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id, Alistair Francis, 2021/10/22
- [PULL 32/33] hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id, Alistair Francis, 2021/10/22
- [PULL 24/33] hw/intc: Remove the Ibex PLIC, Alistair Francis, 2021/10/22
- [PULL 33/33] hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id, Alistair Francis, 2021/10/22
- Re: [PULL 00/33] riscv-to-apply queue, Richard Henderson, 2021/10/22