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[PULL 07/18] target/riscv: Add J-extension into RISC-V
From: |
Alistair Francis |
Subject: |
[PULL 07/18] target/riscv: Add J-extension into RISC-V |
Date: |
Thu, 28 Oct 2021 14:43:31 +1000 |
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 20211025173609.2724490-2-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index a33dc30be8..1cfc6a53a0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -65,6 +65,7 @@
#define RVS RV('S')
#define RVU RV('U')
#define RVH RV('H')
+#define RVJ RV('J')
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
@@ -291,6 +292,7 @@ struct RISCVCPU {
bool ext_s;
bool ext_u;
bool ext_h;
+ bool ext_j;
bool ext_v;
bool ext_zba;
bool ext_zbb;
--
2.31.1
- [PULL 00/18] riscv-to-apply queue, Alistair Francis, 2021/10/28
- [PULL 01/18] hw/riscv: virt: Don't use a macro for the PLIC configuration, Alistair Francis, 2021/10/28
- [PULL 02/18] hw/riscv: boot: Add a PLIC config string function, Alistair Francis, 2021/10/28
- [PULL 04/18] hw/riscv: microchip_pfsoc: Use the PLIC config helper function, Alistair Francis, 2021/10/28
- [PULL 05/18] hw/riscv: virt: Use the PLIC config helper function, Alistair Francis, 2021/10/28
- [PULL 03/18] hw/riscv: sifive_u: Use the PLIC config helper function, Alistair Francis, 2021/10/28
- [PULL 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses, Alistair Francis, 2021/10/28
- [PULL 07/18] target/riscv: Add J-extension into RISC-V,
Alistair Francis <=
- [PULL 08/18] target/riscv: Add CSR defines for RISC-V PM extension, Alistair Francis, 2021/10/28
- [PULL 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode, Alistair Francis, 2021/10/28
- [PULL 10/18] target/riscv: Add J extension state description, Alistair Francis, 2021/10/28
- [PULL 11/18] target/riscv: Print new PM CSRs in QEMU logs, Alistair Francis, 2021/10/28
- [PULL 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions, Alistair Francis, 2021/10/28
- [PULL 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension, Alistair Francis, 2021/10/28
- [PULL 14/18] target/riscv: Allow experimental J-ext to be turned on, Alistair Francis, 2021/10/28
- [PULL 15/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin, Alistair Francis, 2021/10/28
- [PULL 16/18] target/riscv: change the api for RVF/RVD fmin/fmax, Alistair Francis, 2021/10/28