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[PULL 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/
From: |
Alistair Francis |
Subject: |
[PULL 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions |
Date: |
Thu, 28 Oct 2021 14:43:36 +1000 |
From: Alexey Baturo <baturo.alexey@gmail.com>
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211025173609.2724490-7-space.monkey.delivers@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/translate.c | 8 ++++++++
target/riscv/insn_trans/trans_rva.c.inc | 3 +++
target/riscv/insn_trans/trans_rvd.c.inc | 2 ++
target/riscv/insn_trans/trans_rvf.c.inc | 2 ++
target/riscv/insn_trans/trans_rvi.c.inc | 2 ++
5 files changed, 17 insertions(+)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d38f87d718..a5e6fa145d 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -271,6 +271,14 @@ static void gen_jal(DisasContext *ctx, int rd,
target_ulong imm)
ctx->base.is_jmp = DISAS_NORETURN;
}
+/*
+ * Temp stub: generates address adjustment for PointerMasking
+ */
+static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
+{
+ return src;
+}
+
#ifndef CONFIG_USER_ONLY
/* The states of mstatus_fs are:
* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
diff --git a/target/riscv/insn_trans/trans_rva.c.inc
b/target/riscv/insn_trans/trans_rva.c.inc
index 6ea07d89b0..40fe132b04 100644
--- a/target/riscv/insn_trans/trans_rva.c.inc
+++ b/target/riscv/insn_trans/trans_rva.c.inc
@@ -25,6 +25,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp
mop)
if (a->rl) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
+ src1 = gen_pm_adjust_address(ctx, src1);
tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
if (a->aq) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
@@ -44,6 +45,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp
mop)
TCGLabel *l2 = gen_new_label();
src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
+ src1 = gen_pm_adjust_address(ctx, src1);
tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
/*
@@ -84,6 +86,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+ src1 = gen_pm_adjust_address(ctx, src1);
func(dest, src1, src2, ctx->mem_idx, mop);
gen_set_gpr(ctx, a->rd, dest);
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
b/target/riscv/insn_trans/trans_rvd.c.inc
index db9ae15755..64fb0046f7 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -31,6 +31,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = gen_pm_adjust_address(ctx, addr);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ);
@@ -51,6 +52,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = gen_pm_adjust_address(ctx, addr);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ);
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc
b/target/riscv/insn_trans/trans_rvf.c.inc
index bddbd418d9..b5459249c4 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -37,6 +37,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = gen_pm_adjust_address(ctx, addr);
dest = cpu_fpr[a->rd];
tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
@@ -59,6 +60,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = gen_pm_adjust_address(ctx, addr);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index 91dc438a3a..e51dbc41c5 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -144,6 +144,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp
memop)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = gen_pm_adjust_address(ctx, addr);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
gen_set_gpr(ctx, a->rd, dest);
@@ -185,6 +186,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp
memop)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = gen_pm_adjust_address(ctx, addr);
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
return true;
--
2.31.1
- [PULL 02/18] hw/riscv: boot: Add a PLIC config string function, (continued)
- [PULL 02/18] hw/riscv: boot: Add a PLIC config string function, Alistair Francis, 2021/10/28
- [PULL 04/18] hw/riscv: microchip_pfsoc: Use the PLIC config helper function, Alistair Francis, 2021/10/28
- [PULL 05/18] hw/riscv: virt: Use the PLIC config helper function, Alistair Francis, 2021/10/28
- [PULL 03/18] hw/riscv: sifive_u: Use the PLIC config helper function, Alistair Francis, 2021/10/28
- [PULL 06/18] hw/riscv: opentitan: Fixup the PLIC context addresses, Alistair Francis, 2021/10/28
- [PULL 07/18] target/riscv: Add J-extension into RISC-V, Alistair Francis, 2021/10/28
- [PULL 08/18] target/riscv: Add CSR defines for RISC-V PM extension, Alistair Francis, 2021/10/28
- [PULL 09/18] target/riscv: Support CSRs required for RISC-V PM extension except for the h-mode, Alistair Francis, 2021/10/28
- [PULL 10/18] target/riscv: Add J extension state description, Alistair Francis, 2021/10/28
- [PULL 11/18] target/riscv: Print new PM CSRs in QEMU logs, Alistair Francis, 2021/10/28
- [PULL 12/18] target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions,
Alistair Francis <=
- [PULL 13/18] target/riscv: Implement address masking functions required for RISC-V Pointer Masking extension, Alistair Francis, 2021/10/28
- [PULL 14/18] target/riscv: Allow experimental J-ext to be turned on, Alistair Francis, 2021/10/28
- [PULL 15/18] softfloat: add APIs to handle alternative sNaN propagation for fmax/fmin, Alistair Francis, 2021/10/28
- [PULL 16/18] target/riscv: change the api for RVF/RVD fmin/fmax, Alistair Francis, 2021/10/28
[PULL 17/18] target/riscv: fix VS interrupts forwarding to HS, Alistair Francis, 2021/10/28
[PULL 18/18] target/riscv: remove force HS exception, Alistair Francis, 2021/10/28