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[PATCH 44/62] target/arm: Add ARMMMUIdx_Phys_{S,NS}
From: |
Richard Henderson |
Subject: |
[PATCH 44/62] target/arm: Add ARMMMUIdx_Phys_{S,NS} |
Date: |
Sun, 3 Jul 2022 13:54:01 +0530 |
Not yet used, but add mmu indexes for 1-1 mapping
to physical addresses.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 4 ++++
target/arm/ptw.c | 9 +++++++++
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index 6f702f58d9..931808f2e7 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -40,6 +40,6 @@ struct PageEntryExtra {
};
#endif
-#define NB_MMU_MODES 8
+#define NB_MMU_MODES 10
#endif
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index dd577a08bc..c5aec164ba 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2934,6 +2934,10 @@ typedef enum ARMMMUIdx {
ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A,
ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A,
+ /* TLBs with 1-1 mapping to the physical address spaces. */
+ ARMMMUIdx_Phys_NS = 8 | ARM_MMU_IDX_A,
+ ARMMMUIdx_Phys_S = 9 | ARM_MMU_IDX_A,
+
/*
* These are not allocated TLBs and are used only for AT system
* instructions or for the first stage of an S12 page table walk.
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 3a098882a6..7510a9276a 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -179,6 +179,11 @@ static bool regime_translation_disabled(CPUARMState *env,
ARMMMUIdx mmu_idx,
case ARMMMUIdx_E3:
break;
+ case ARMMMUIdx_Phys_NS:
+ case ARMMMUIdx_Phys_S:
+ /* No translation for physical address spaces. */
+ return true;
+
default:
g_assert_not_reached();
}
@@ -2284,6 +2289,8 @@ static bool get_phys_addr_disabled(CPUARMState *env,
target_ulong address,
switch (mmu_idx) {
case ARMMMUIdx_Stage2:
case ARMMMUIdx_Stage2_S:
+ case ARMMMUIdx_Phys_NS:
+ case ARMMMUIdx_Phys_S:
memattr = 0x00; /* unused, but Device, nGnRnE */
shareability = 0; /* unused, but non-shareable */
break;
@@ -2574,6 +2581,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
is_secure = arm_is_secure_below_el3(env);
break;
case ARMMMUIdx_Stage2:
+ case ARMMMUIdx_Phys_NS:
case ARMMMUIdx_MPrivNegPri:
case ARMMMUIdx_MUserNegPri:
case ARMMMUIdx_MPriv:
@@ -2582,6 +2590,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
break;
case ARMMMUIdx_E3:
case ARMMMUIdx_Stage2_S:
+ case ARMMMUIdx_Phys_S:
case ARMMMUIdx_MSPrivNegPri:
case ARMMMUIdx_MSUserNegPri:
case ARMMMUIdx_MSPriv:
--
2.34.1
- [PATCH 33/62] target/arm: Fold secure and non-secure a-profile mmu indexes, (continued)
- [PATCH 33/62] target/arm: Fold secure and non-secure a-profile mmu indexes, Richard Henderson, 2022/07/03
- [PATCH 34/62] target/arm: Reorg regime_translation_disabled, Richard Henderson, 2022/07/03
- [PATCH 35/62] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M, Richard Henderson, 2022/07/03
- [PATCH 36/62] target/arm: Introduce arm_hcr_el2_eff_secstate, Richard Henderson, 2022/07/03
- [PATCH 37/62] target/arm: Hoist read of *is_secure in S1_ptw_translate, Richard Henderson, 2022/07/03
- [PATCH 38/62] target/arm: Fix S2 disabled check in S1_ptw_translate, Richard Henderson, 2022/07/03
- [PATCH 39/62] target/arm: Remove env argument from combined_attrs_fwb, Richard Henderson, 2022/07/03
- [PATCH 40/62] target/arm: Pass HCR to attribute subroutines., Richard Henderson, 2022/07/03
- [PATCH 41/62] target/arm: Fix ATS12NSO* from S PL1, Richard Henderson, 2022/07/03
- [PATCH 42/62] target/arm: Split out get_phys_addr_disabled, Richard Henderson, 2022/07/03
- [PATCH 44/62] target/arm: Add ARMMMUIdx_Phys_{S,NS},
Richard Henderson <=
- [PATCH 43/62] target/arm: Reorg get_phys_addr_disabled, Richard Henderson, 2022/07/03
- [PATCH 45/62] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx, Richard Henderson, 2022/07/03
- [PATCH 46/62] target/arm: Use softmmu tlbs for page table walking, Richard Henderson, 2022/07/03
- [PATCH 47/62] target/arm: Hoist check for disabled stage2 translation., Richard Henderson, 2022/07/03
- [PATCH 48/62] target/arm: Split out get_phys_addr_twostage, Richard Henderson, 2022/07/03
- [PATCH 49/62] target/arm: Use bool consistently for get_phys_addr subroutines, Richard Henderson, 2022/07/03
- [PATCH 50/62] target/arm: Only use ARMMMUIdx_Stage1* for two-stage translation, Richard Henderson, 2022/07/03
- [PATCH 52/62] target/arm: Add isar predicates for FEAT_HAFDBS, Richard Henderson, 2022/07/03
- [PATCH 54/62] target/arm: Split out S1TranslateResult type, Richard Henderson, 2022/07/03
- [PATCH 55/62] target/arm: Move be test for regime into S1TranslateResult, Richard Henderson, 2022/07/03