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[PATCH 50/62] target/arm: Only use ARMMMUIdx_Stage1* for two-stage trans
From: |
Richard Henderson |
Subject: |
[PATCH 50/62] target/arm: Only use ARMMMUIdx_Stage1* for two-stage translation |
Date: |
Sun, 3 Jul 2022 13:54:07 +0530 |
If stage2 is disabled, we do not need to adjust mmu_idx.
Below, we'll use get_phys_addr_lpae and not recurse.
Adjust regime_is_user so that it can be used for E10_0.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 9 +--------
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index a2c441d947..e42286b4c1 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -90,6 +90,7 @@ static bool regime_translation_big_endian(CPUARMState *env,
ARMMMUIdx mmu_idx)
static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
{
switch (mmu_idx) {
+ case ARMMMUIdx_E10_0:
case ARMMMUIdx_E20_0:
case ARMMMUIdx_Stage1_E0:
case ARMMMUIdx_MUser:
@@ -99,10 +100,6 @@ static bool regime_is_user(CPUARMState *env, ARMMMUIdx
mmu_idx)
return true;
default:
return false;
- case ARMMMUIdx_E10_0:
- case ARMMMUIdx_E10_1:
- case ARMMMUIdx_E10_1_PAN:
- g_assert_not_reached();
}
}
@@ -2530,10 +2527,6 @@ bool get_phys_addr_with_secure(CPUARMState *env,
target_ulong address,
s1_mmu_idx, is_secure,
result, fi);
}
- /*
- * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
- */
- mmu_idx = s1_mmu_idx;
}
/*
--
2.34.1
- [PATCH 40/62] target/arm: Pass HCR to attribute subroutines., (continued)
- [PATCH 40/62] target/arm: Pass HCR to attribute subroutines., Richard Henderson, 2022/07/03
- [PATCH 41/62] target/arm: Fix ATS12NSO* from S PL1, Richard Henderson, 2022/07/03
- [PATCH 42/62] target/arm: Split out get_phys_addr_disabled, Richard Henderson, 2022/07/03
- [PATCH 44/62] target/arm: Add ARMMMUIdx_Phys_{S,NS}, Richard Henderson, 2022/07/03
- [PATCH 43/62] target/arm: Reorg get_phys_addr_disabled, Richard Henderson, 2022/07/03
- [PATCH 45/62] target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx, Richard Henderson, 2022/07/03
- [PATCH 46/62] target/arm: Use softmmu tlbs for page table walking, Richard Henderson, 2022/07/03
- [PATCH 47/62] target/arm: Hoist check for disabled stage2 translation., Richard Henderson, 2022/07/03
- [PATCH 48/62] target/arm: Split out get_phys_addr_twostage, Richard Henderson, 2022/07/03
- [PATCH 49/62] target/arm: Use bool consistently for get_phys_addr subroutines, Richard Henderson, 2022/07/03
- [PATCH 50/62] target/arm: Only use ARMMMUIdx_Stage1* for two-stage translation,
Richard Henderson <=
- [PATCH 52/62] target/arm: Add isar predicates for FEAT_HAFDBS, Richard Henderson, 2022/07/03
- [PATCH 54/62] target/arm: Split out S1TranslateResult type, Richard Henderson, 2022/07/03
- [PATCH 55/62] target/arm: Move be test for regime into S1TranslateResult, Richard Henderson, 2022/07/03
- [PATCH 51/62] target/arm: Add ptw_idx argument to S1_ptw_translate, Richard Henderson, 2022/07/03
- [PATCH 53/62] target/arm: Extract HA and HD in aa64_va_parameters, Richard Henderson, 2022/07/03
- [PATCH 56/62] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw, Richard Henderson, 2022/07/03
- [PATCH 57/62] target/arm: Add ARMFault_UnsuppAtomicUpdate, Richard Henderson, 2022/07/03
- [PATCH 58/62] target/arm: Remove loop from get_phys_addr_lpae, Richard Henderson, 2022/07/03
- [PATCH 59/62] target/arm: Fix fault reporting in get_phys_addr_lpae, Richard Henderson, 2022/07/03
- [PATCH 60/62] target/arm: Don't shift attrs in get_phys_addr_lpae, Richard Henderson, 2022/07/03