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[PATCH v2 07/11] target/openrisc: Add interrupted CPU to log
From: |
Stafford Horne |
Subject: |
[PATCH v2 07/11] target/openrisc: Add interrupted CPU to log |
Date: |
Mon, 4 Jul 2022 06:28:19 +0900 |
When we are tracing it's helpful to know which CPU's are getting
interrupted, att that detail to the log line.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/interrupt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index e5724f5371..c31c6f12c4 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -83,7 +83,9 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
[EXCP_TRAP] = "TRAP",
};
- qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]);
+ qemu_log_mask(CPU_LOG_INT, "CPU: %d INT: %s\n",
+ cs->cpu_index,
+ int_name[exception]);
hwaddr vect_pc = exception << 8;
if (env->cpucfgr & CPUCFGR_EVBARP) {
--
2.36.1
[PATCH v2 04/11] hw/openrisc: Add the OpenRISC virtual machine, Stafford Horne, 2022/07/03
[PATCH v2 05/11] hw/openrisc: Add PCI bus support to virt, Stafford Horne, 2022/07/03
[PATCH v2 06/11] hw/openrisc: Initialize timer time at startup, Stafford Horne, 2022/07/03
[PATCH v2 07/11] target/openrisc: Add interrupted CPU to log,
Stafford Horne <=
[PATCH v2 08/11] target/openrisc: Enable MTTCG, Stafford Horne, 2022/07/03
[PATCH v2 09/11] target/openrisc: Interrupt handling fixes, Stafford Horne, 2022/07/03
[PATCH v2 10/11] hw/openrisc: virt: pass random seed to fdt, Stafford Horne, 2022/07/03
[PATCH v2 11/11] docs/system: openrisc: Add OpenRISC documentation, Stafford Horne, 2022/07/03