Re: [PATCH v2 09/11] target/openrisc: Interrupt handling fixes

[Richard Henderson]

On 7/4/22 02:58, Stafford Horne wrote:
> When running SMP systems we sometimes were seeing lockups where
> IPI interrupts were being raised by never handled.
>
> This looks to be caused by 2 issues in the openrisc interrupt handling
> logic.
>
>   1. After clearing an interrupt the openrisc_cpu_set_irq handler will
>      always clear PICSR.  This is not correct as masked interrupts
>      should still be visible in PICSR.
>   2. After setting PICMR (mask register) and exposed interrupts should
>      cause an interrupt to be raised.  This was not being done so add it.
>
> This patch fixes both issues.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~