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[PULL 01/45] target/arm: Handle SME in aarch64_cpu_dump_state
From: |
Peter Maydell |
Subject: |
[PULL 01/45] target/arm: Handle SME in aarch64_cpu_dump_state |
Date: |
Mon, 11 Jul 2022 14:57:06 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Dump SVCR, plus use the correct access check for Streaming Mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ae6dca2f010..9c58be8b146 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -878,6 +878,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
int i;
int el = arm_current_el(env);
const char *ns_status;
+ bool sve;
qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
for (i = 0; i < 32; i++) {
@@ -904,6 +905,12 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
el,
psr & PSTATE_SP ? 'h' : 't');
+ if (cpu_isar_feature(aa64_sme, cpu)) {
+ qemu_fprintf(f, " SVCR=%08" PRIx64 " %c%c",
+ env->svcr,
+ (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'),
+ (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-'));
+ }
if (cpu_isar_feature(aa64_bti, cpu)) {
qemu_fprintf(f, " BTYPE=%d", (psr & PSTATE_BTYPE) >> 10);
}
@@ -918,7 +925,15 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
int flags)
qemu_fprintf(f, " FPCR=%08x FPSR=%08x\n",
vfp_get_fpcr(env), vfp_get_fpsr(env));
- if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) {
+ if (cpu_isar_feature(aa64_sme, cpu) && FIELD_EX64(env->svcr, SVCR, SM)) {
+ sve = sme_exception_el(env, el) == 0;
+ } else if (cpu_isar_feature(aa64_sve, cpu)) {
+ sve = sve_exception_el(env, el) == 0;
+ } else {
+ sve = false;
+ }
+
+ if (sve) {
int j, zcr_len = sve_vqm1_for_el(env, el);
for (i = 0; i <= FFR_PRED_NUM; i++) {
--
2.25.1
- [PULL 00/45] target-arm queue, Peter Maydell, 2022/07/11
- [PULL 05/45] target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming, Peter Maydell, 2022/07/11
- [PULL 04/45] target/arm: Mark ADR as non-streaming, Peter Maydell, 2022/07/11
- [PULL 11/45] target/arm: Mark gather/scatter load/store as non-streaming, Peter Maydell, 2022/07/11
- [PULL 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active, Peter Maydell, 2022/07/11
- [PULL 01/45] target/arm: Handle SME in aarch64_cpu_dump_state,
Peter Maydell <=
- [PULL 07/45] target/arm: Mark PMULL, FMMLA as non-streaming, Peter Maydell, 2022/07/11
- [PULL 10/45] target/arm: Mark string/histo/crypto as non-streaming, Peter Maydell, 2022/07/11
- [PULL 23/45] target/arm: Implement SME ADDHA, ADDVA, Peter Maydell, 2022/07/11
- [PULL 18/45] target/arm: Implement SME ZERO, Peter Maydell, 2022/07/11
- [PULL 14/45] target/arm: Mark LD1RO as non-streaming, Peter Maydell, 2022/07/11
- [PULL 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming, Peter Maydell, 2022/07/11
- [PULL 25/45] target/arm: Implement BFMOPA, BFMOPS, Peter Maydell, 2022/07/11
- [PULL 22/45] target/arm: Implement SME LDR, STR, Peter Maydell, 2022/07/11
- [PULL 27/45] target/arm: Implement SME integer outer product, Peter Maydell, 2022/07/11
- [PULL 29/45] target/arm: Implement REVD, Peter Maydell, 2022/07/11