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[PULL 22/45] target/arm: Implement SME LDR, STR
From: |
Peter Maydell |
Subject: |
[PULL 22/45] target/arm: Implement SME LDR, STR |
Date: |
Mon, 11 Jul 2022 14:57:27 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
We can reuse the SVE functions for LDR and STR, passing in the
base of the ZA vector and a zero offset.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/sme.decode | 7 +++++++
target/arm/translate-sme.c | 24 ++++++++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/target/arm/sme.decode b/target/arm/sme.decode
index 900e3f2a077..f1ebd857a57 100644
--- a/target/arm/sme.decode
+++ b/target/arm/sme.decode
@@ -46,3 +46,10 @@ LDST1 1110000 0 esz:2 st:1 rm:5 v:1 .. pg:3 rn:5 0
za_imm:4 \
&ldst rs=%mova_rs
LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn:5 0 za_imm:4 \
&ldst esz=4 rs=%mova_rs
+
+&ldstr rv rn imm
+@ldstr ....... ... . ...... .. ... rn:5 . imm:4 \
+ &ldstr rv=%mova_rs
+
+LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr
+STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr
diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c
index 42d14b883ab..35c26448125 100644
--- a/target/arm/translate-sme.c
+++ b/target/arm/translate-sme.c
@@ -243,3 +243,27 @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
tcg_temp_free_i64(addr);
return true;
}
+
+typedef void GenLdStR(DisasContext *, TCGv_ptr, int, int, int, int);
+
+static bool do_ldst_r(DisasContext *s, arg_ldstr *a, GenLdStR *fn)
+{
+ int svl = streaming_vec_reg_size(s);
+ int imm = a->imm;
+ TCGv_ptr base;
+
+ if (!sme_za_enabled_check(s)) {
+ return true;
+ }
+
+ /* ZA[n] equates to ZA0H.B[n]. */
+ base = get_tile_rowcol(s, MO_8, a->rv, imm, false);
+
+ fn(s, base, 0, svl, a->rn, imm * svl);
+
+ tcg_temp_free_ptr(base);
+ return true;
+}
+
+TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr)
+TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str)
--
2.25.1
- [PULL 11/45] target/arm: Mark gather/scatter load/store as non-streaming, (continued)
- [PULL 11/45] target/arm: Mark gather/scatter load/store as non-streaming, Peter Maydell, 2022/07/11
- [PULL 03/45] target/arm: Trap non-streaming usage when Streaming SVE is active, Peter Maydell, 2022/07/11
- [PULL 01/45] target/arm: Handle SME in aarch64_cpu_dump_state, Peter Maydell, 2022/07/11
- [PULL 07/45] target/arm: Mark PMULL, FMMLA as non-streaming, Peter Maydell, 2022/07/11
- [PULL 10/45] target/arm: Mark string/histo/crypto as non-streaming, Peter Maydell, 2022/07/11
- [PULL 23/45] target/arm: Implement SME ADDHA, ADDVA, Peter Maydell, 2022/07/11
- [PULL 18/45] target/arm: Implement SME ZERO, Peter Maydell, 2022/07/11
- [PULL 14/45] target/arm: Mark LD1RO as non-streaming, Peter Maydell, 2022/07/11
- [PULL 13/45] target/arm: Mark LDFF1 and LDNF1 as non-streaming, Peter Maydell, 2022/07/11
- [PULL 25/45] target/arm: Implement BFMOPA, BFMOPS, Peter Maydell, 2022/07/11
- [PULL 22/45] target/arm: Implement SME LDR, STR,
Peter Maydell <=
- [PULL 27/45] target/arm: Implement SME integer outer product, Peter Maydell, 2022/07/11
- [PULL 29/45] target/arm: Implement REVD, Peter Maydell, 2022/07/11
- [PULL 15/45] target/arm: Add SME enablement checks, Peter Maydell, 2022/07/11
- [PULL 12/45] target/arm: Mark gather prefetch as non-streaming, Peter Maydell, 2022/07/11
- [PULL 02/45] target/arm: Add infrastructure for disas_sme, Peter Maydell, 2022/07/11
- [PULL 09/45] target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming, Peter Maydell, 2022/07/11
- [PULL 06/45] target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming, Peter Maydell, 2022/07/11
- [PULL 16/45] target/arm: Handle SME in sve_access_check, Peter Maydell, 2022/07/11
- [PULL 19/45] target/arm: Implement SME MOVA, Peter Maydell, 2022/07/11
- [PULL 21/45] target/arm: Export unpredicated ld/st from translate-sve.c, Peter Maydell, 2022/07/11