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[PATCH 01/11] target/arm: Add ARM_FEATURE_V8_R
From: |
Tobias Roehmel |
Subject: |
[PATCH 01/11] target/arm: Add ARM_FEATURE_V8_R |
Date: |
Thu, 14 Jul 2022 16:53:45 +0200 |
From: Tobias Röhmel <quic_trohmel@quicinc.com>
This flag is necessary to add features for the Cortex-R52.
Signed-off-by: Tobias Röhmel <quic_trohmel@quicinc.com>
---
target/arm/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index df677b2d5d..86e06116a9 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2287,6 +2287,7 @@ enum arm_features {
ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
ARM_FEATURE_M_MAIN, /* M profile Main Extension */
ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
+ ARM_FEATURE_V8_R,
};
static inline int arm_feature(CPUARMState *env, int feature)
--
2.25.1
- [PATCH 00/11] Add Cortex-R52, Tobias Roehmel, 2022/07/14
- [PATCH 01/11] target/arm: Add ARM_FEATURE_V8_R,
Tobias Roehmel <=
- [PATCH 04/11] target/arm: Make RVBAR available for non AARCH64 CPUs, Tobias Roehmel, 2022/07/14
- [PATCH 06/11] target/arm: Add ARMCacheAttrs to the signature of pmsav8_mpu_lookup, Tobias Roehmel, 2022/07/14
- [PATCH 09/11] target/arm: Add PMSAv8r functionality, Tobias Roehmel, 2022/07/14
- [PATCH 08/11] target/arm Add PMSAv8r registers, Tobias Roehmel, 2022/07/14
- [PATCH 05/11] target/arm: Make stage_2_format for cache attributes optional, Tobias Roehmel, 2022/07/14
- [PATCH 03/11] target/arm: Add v8R MIDR register, Tobias Roehmel, 2022/07/14
- [PATCH 07/11] target/arm: Enable TTBCR_EAE for ARM_FEATURE_V8_R, Tobias Roehmel, 2022/07/14