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[PATCH v3 08/11] target/openrisc: Enable MTTCG
From: |
Stafford Horne |
Subject: |
[PATCH v3 08/11] target/openrisc: Enable MTTCG |
Date: |
Sat, 30 Jul 2022 08:01:14 +0900 |
This patch enables multithread TCG for OpenRISC. Since the or1k shared
syncrhonized timer can be updated from each vCPU via helpers we use a
mutex to synchronize updates.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
Since v2:
- Removed cpu_openrisc_timer_has_advanced lock optimization, measuring revealed
it did not help much.
configs/targets/or1k-softmmu.mak | 1 +
target/openrisc/cpu.h | 2 ++
target/openrisc/sys_helper.c | 7 ++++++-
3 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/configs/targets/or1k-softmmu.mak b/configs/targets/or1k-softmmu.mak
index 263e970870..432f855a30 100644
--- a/configs/targets/or1k-softmmu.mak
+++ b/configs/targets/or1k-softmmu.mak
@@ -1,3 +1,4 @@
TARGET_ARCH=openrisc
+TARGET_SUPPORTS_MTTCG=y
TARGET_BIG_ENDIAN=y
TARGET_NEED_FDT=y
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index b9584f10d4..1d5efa5ca2 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -25,6 +25,8 @@
#include "hw/core/cpu.h"
#include "qom/object.h"
+#define TCG_GUEST_DEFAULT_MO (0)
+
#define TYPE_OPENRISC_CPU "or1k-cpu"
OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 48674231e7..da88ad9e77 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -145,6 +145,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr,
target_ulong rb)
break;
case TO_SPR(10, 0): /* TTMR */
{
+ qemu_mutex_lock_iothread();
if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
switch (rb & TTMR_M) {
case TIMER_NONE:
@@ -168,14 +169,16 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong
spr, target_ulong rb)
env->ttmr = rb & ~TTMR_IP;
cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
}
-
cpu_openrisc_timer_update(cpu);
+ qemu_mutex_unlock_iothread();
}
break;
case TO_SPR(10, 1): /* TTCR */
+ qemu_mutex_lock_iothread();
cpu_openrisc_count_set(cpu, rb);
cpu_openrisc_timer_update(cpu);
+ qemu_mutex_unlock_iothread();
break;
#endif
@@ -303,7 +306,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
target_ulong rd,
return env->ttmr;
case TO_SPR(10, 1): /* TTCR */
+ qemu_mutex_lock_iothread();
cpu_openrisc_count_update(cpu);
+ qemu_mutex_unlock_iothread();
return cpu_openrisc_count_get(cpu);
#endif
--
2.37.1
- [PATCH v3 04/11] hw/openrisc: Add the OpenRISC virtual machine, (continued)
- [PATCH v3 04/11] hw/openrisc: Add the OpenRISC virtual machine, Stafford Horne, 2022/07/29
- [PATCH v3 05/11] hw/openrisc: Add PCI bus support to virt, Stafford Horne, 2022/07/29
- [PATCH v3 06/11] hw/openrisc: Initialize timer time at startup, Stafford Horne, 2022/07/29
- [PATCH v3 03/11] goldfish_rtc: Add big-endian property, Stafford Horne, 2022/07/29
- [PATCH v3 07/11] target/openrisc: Add interrupted CPU to log, Stafford Horne, 2022/07/29
- [PATCH v3 10/11] hw/openrisc: virt: pass random seed to fdt, Stafford Horne, 2022/07/29
- [PATCH v3 09/11] target/openrisc: Interrupt handling fixes, Stafford Horne, 2022/07/29
- [PATCH v3 11/11] docs/system: openrisc: Add OpenRISC documentation, Stafford Horne, 2022/07/29
- [PATCH v3 08/11] target/openrisc: Enable MTTCG,
Stafford Horne <=