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[PULL 05/44] hw/riscv: virt: pass random seed to fdt
From: |
Alistair Francis |
Subject: |
[PULL 05/44] hw/riscv: virt: pass random seed to fdt |
Date: |
Wed, 7 Sep 2022 10:03:14 +0200 |
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
If the FDT contains /chosen/rng-seed, then the Linux RNG will use it to
initialize early. Set this using the usual guest random number
generation function. This is confirmed to successfully initialize the
RNG on Linux 5.19-rc2.
Cc: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220613115810.178210-1-Jason@zx2c4.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
hw/riscv/virt.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index bc424dd2f5..f2ce5663a4 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
+#include "qemu/guest-random.h"
#include "qapi/error.h"
#include "hw/boards.h"
#include "hw/loader.h"
@@ -998,6 +999,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry
*memmap,
MachineState *mc = MACHINE(s);
uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1;
uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1;
+ uint8_t rng_seed[32];
if (mc->dtb) {
mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
@@ -1046,6 +1048,10 @@ update_bootargs:
if (cmdline && *cmdline) {
qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline);
}
+
+ /* Pass seed to RNG */
+ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
+ qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed,
sizeof(rng_seed));
}
static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
--
2.37.2
- [PULL 00/44] riscv-to-apply queue, Alistair Francis, 2022/09/07
- [PULL 04/44] target/riscv: move zmmul out of the experimental properties, Alistair Francis, 2022/09/07
- [PULL 06/44] target/riscv: Add check for supported privilege mode combinations, Alistair Francis, 2022/09/07
- [PULL 03/44] target/riscv: fix shifts shamt value for rv128c, Alistair Francis, 2022/09/07
- [PULL 13/44] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V, Alistair Francis, 2022/09/07
- [PULL 05/44] hw/riscv: virt: pass random seed to fdt,
Alistair Francis <=
- [PULL 02/44] target/riscv: Force disable extensions if priv spec version does not match, Alistair Francis, 2022/09/07
- [PULL 08/44] target/riscv: Fix checkpatch warning may triggered in csr_ops table, Alistair Francis, 2022/09/07
- [PULL 07/44] target/riscv: H extension depends on I extension, Alistair Francis, 2022/09/07
- [PULL 09/44] target/riscv: Add check for csrs existed with U extension, Alistair Francis, 2022/09/07
- [PULL 10/44] target/riscv: Fix checks in hmode/hmode32, Alistair Francis, 2022/09/07
- [PULL 12/44] roms/opensbi: Upgrade from v1.0 to v1.1, Alistair Francis, 2022/09/07
- [PULL 01/44] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt(), Alistair Francis, 2022/09/07
- [PULL 11/44] target/riscv: Simplify the check in hmode to reuse the check in riscv_csrrw_check, Alistair Francis, 2022/09/07
- [PULL 15/44] target/riscv: rvv: Add mask agnostic for vv instructions, Alistair Francis, 2022/09/07
- [PULL 14/44] docs: List kvm as a supported accelerator on RISC-V, Alistair Francis, 2022/09/07