---
target/riscv/cpu-config.h | 148 ++++++++++++++++++++++++++++++++++++++
target/riscv/cpu.h | 114 +----------------------------
target/riscv/translate.c | 27 +------
3 files changed, 151 insertions(+), 138 deletions(-)
create mode 100644 target/riscv/cpu-config.h
diff --git a/target/riscv/cpu-config.h b/target/riscv/cpu-config.h
new file mode 100644
index 0000000000..ca368af0b2
--- /dev/null
+++ b/target/riscv/cpu-config.h
@@ -0,0 +1,148 @@
+/*
+ * QEMU RISC-V CPU Config
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef RISCV_CPU_CONFIG_H
+#define RISCV_CPU_CONFIG_H
+
+/*
+ * map is a 16-bit bitmap: the most significant set bit in map is the maximum
+ * satp mode that is supported. It may be chosen by the user and must respect
+ * what qemu implements (valid_1_10_32/64) and what the hw is capable of
+ * (supported bitmap below).
+ *
+ * init is a 16-bit bitmap used to make sure the user selected a correct
+ * configuration as per the specification.
+ *
+ * supported is a 16-bit bitmap used to reflect the hw capabilities.
+ */
+typedef struct {
+ uint16_t map, init, supported;
+} RISCVSATPMap;
+
+struct RISCVCPUConfig {
+ bool ext_zba;
+ bool ext_zbb;
+ bool ext_zbc;
+ bool ext_zbkb;
+ bool ext_zbkc;
+ bool ext_zbkx;
+ bool ext_zbs;
+ bool ext_zca;
+ bool ext_zcb;
+ bool ext_zcd;
+ bool ext_zce;
+ bool ext_zcf;
+ bool ext_zcmp;
+ bool ext_zcmt;
+ bool ext_zk;
+ bool ext_zkn;
+ bool ext_zknd;
+ bool ext_zkne;
+ bool ext_zknh;
+ bool ext_zkr;
+ bool ext_zks;
+ bool ext_zksed;
+ bool ext_zksh;
+ bool ext_zkt;
+ bool ext_ifencei;
+ bool ext_icsr;
+ bool ext_icbom;
+ bool ext_icboz;
+ bool ext_zicond;
+ bool ext_zihintpause;
+ bool ext_smstateen;
+ bool ext_sstc;
+ bool ext_svadu;
+ bool ext_svinval;
+ bool ext_svnapot;
+ bool ext_svpbmt;
+ bool ext_zdinx;
+ bool ext_zawrs;
+ bool ext_zfh;
+ bool ext_zfhmin;
+ bool ext_zfinx;
+ bool ext_zhinx;
+ bool ext_zhinxmin;
+ bool ext_zve32f;
+ bool ext_zve64f;
+ bool ext_zve64d;
+ bool ext_zmmul;
+ bool ext_zvfh;
+ bool ext_zvfhmin;
+ bool ext_smaia;
+ bool ext_ssaia;
+ bool ext_sscofpmf;
+ bool rvv_ta_all_1s;
+ bool rvv_ma_all_1s;
+
+ uint32_t mvendorid;
+ uint64_t marchid;
+ uint64_t mimpid;
+
+ /* Vendor-specific custom extensions */
+ bool ext_xtheadba;
+ bool ext_xtheadbb;
+ bool ext_xtheadbs;
+ bool ext_xtheadcmo;
+ bool ext_xtheadcondmov;
+ bool ext_xtheadfmemidx;
+ bool ext_xtheadfmv;
+ bool ext_xtheadmac;
+ bool ext_xtheadmemidx;
+ bool ext_xtheadmempair;
+ bool ext_xtheadsync;
+ bool ext_XVentanaCondOps;
+
+ uint8_t pmu_num;
+ char *priv_spec;
+ char *user_spec;
+ char *bext_spec;
+ char *vext_spec;
+ uint16_t vlen;
+ uint16_t elen;
+ uint16_t cbom_blocksize;
+ uint16_t cboz_blocksize;
+ bool mmu;
+ bool pmp;
+ bool epmp;
+ bool debug;
+ bool misa_w;
+
+ bool short_isa_string;
+
+#ifndef CONFIG_USER_ONLY
+ RISCVSATPMap satp_mode;
+#endif
+};
+
+typedef struct RISCVCPUConfig RISCVCPUConfig;
+
+/* Helper functions to test for extensions. */
+
+static inline bool always_true_p(const RISCVCPUConfig *cfg
__attribute__((__unused__)))
+{
+ return true;
+}
+
+static inline bool has_xthead_p(const RISCVCPUConfig *cfg)
+{
+ return cfg->ext_xtheadba || cfg->ext_xtheadbb ||
+ cfg->ext_xtheadbs || cfg->ext_xtheadcmo ||
+ cfg->ext_xtheadcondmov ||
+ cfg->ext_xtheadfmemidx || cfg->ext_xtheadfmv ||
+ cfg->ext_xtheadmac || cfg->ext_xtheadmemidx ||
+ cfg->ext_xtheadmempair || cfg->ext_xtheadsync;
+}
+
+#define MATERIALISE_EXT_PREDICATE(ext) \
+ static inline bool has_ ## ext ## _p(const RISCVCPUConfig *cfg) \
+ { \
+ return cfg->ext_ ## ext ; \
+ }
+
+MATERIALISE_EXT_PREDICATE(XVentanaCondOps)
+
+#endif /* RISCV_CPU_CONFIG_H */
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index de7e43126a..895a307bad 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -28,6 +28,7 @@
#include "qemu/int128.h"
#include "cpu_bits.h"
#include "qapi/qapi-types-common.h"
+#include "cpu-config.h"
#include "cpu-qom.h"
#define TCG_GUEST_DEFAULT_MO 0
@@ -368,119 +369,6 @@ struct CPUArchState {
uint64_t kvm_timer_frequency;
};
-/*
- * map is a 16-bit bitmap: the most significant set bit in map is the maximum
- * satp mode that is supported. It may be chosen by the user and must respect
- * what qemu implements (valid_1_10_32/64) and what the hw is capable of
- * (supported bitmap below).
- *
- * init is a 16-bit bitmap used to make sure the user selected a correct
- * configuration as per the specification.
- *
- * supported is a 16-bit bitmap used to reflect the hw capabilities.
- */
-typedef struct {
- uint16_t map, init, supported;
-} RISCVSATPMap;
-
-struct RISCVCPUConfig {
- bool ext_zba;
- bool ext_zbb;
- bool ext_zbc;
- bool ext_zbkb;
- bool ext_zbkc;
- bool ext_zbkx;
- bool ext_zbs;
- bool ext_zca;
- bool ext_zcb;
- bool ext_zcd;
- bool ext_zce;
- bool ext_zcf;
- bool ext_zcmp;
- bool ext_zcmt;
- bool ext_zk;
- bool ext_zkn;
- bool ext_zknd;
- bool ext_zkne;
- bool ext_zknh;
- bool ext_zkr;
- bool ext_zks;
- bool ext_zksed;
- bool ext_zksh;
- bool ext_zkt;
- bool ext_ifencei;
- bool ext_icsr;
- bool ext_icbom;
- bool ext_icboz;
- bool ext_zicond;
- bool ext_zihintpause;
- bool ext_smstateen;
- bool ext_sstc;
- bool ext_svadu;
- bool ext_svinval;
- bool ext_svnapot;
- bool ext_svpbmt;
- bool ext_zdinx;
- bool ext_zawrs;
- bool ext_zfh;
- bool ext_zfhmin;
- bool ext_zfinx;
- bool ext_zhinx;
- bool ext_zhinxmin;
- bool ext_zve32f;
- bool ext_zve64f;
- bool ext_zve64d;
- bool ext_zmmul;
- bool ext_zvfh;
- bool ext_zvfhmin;
- bool ext_smaia;
- bool ext_ssaia;
- bool ext_sscofpmf;
- bool rvv_ta_all_1s;
- bool rvv_ma_all_1s;
-
- uint32_t mvendorid;
- uint64_t marchid;
- uint64_t mimpid;
-
- /* Vendor-specific custom extensions */
- bool ext_xtheadba;
- bool ext_xtheadbb;
- bool ext_xtheadbs;
- bool ext_xtheadcmo;
- bool ext_xtheadcondmov;
- bool ext_xtheadfmemidx;
- bool ext_xtheadfmv;
- bool ext_xtheadmac;
- bool ext_xtheadmemidx;
- bool ext_xtheadmempair;
- bool ext_xtheadsync;
- bool ext_XVentanaCondOps;
-
- uint8_t pmu_num;
- char *priv_spec;
- char *user_spec;
- char *bext_spec;
- char *vext_spec;
- uint16_t vlen;
- uint16_t elen;
- uint16_t cbom_blocksize;
- uint16_t cboz_blocksize;
- bool mmu;
- bool pmp;
- bool epmp;
- bool debug;
- bool misa_w;
-
- bool short_isa_string;
-
-#ifndef CONFIG_USER_ONLY
- RISCVSATPMap satp_mode;
-#endif
-};
-
-typedef struct RISCVCPUConfig RISCVCPUConfig;
-
/*
* RISCVCPU:
* @env: #CPURISCVState
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 928da0d3f0..2697cc26d0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -119,29 +119,6 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
return ctx->misa_ext & ext;
}
-static bool always_true_p(DisasContext *ctx __attribute__((__unused__)))
-{
- return true;
-}
-
-static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
-{
- return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
- ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
- ctx->cfg_ptr->ext_xtheadcondmov ||
- ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv ||
- ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx ||
- ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync;
-}
-
-#define MATERIALISE_EXT_PREDICATE(ext) \
- static bool has_ ## ext ## _p(DisasContext *ctx) \
- { \
- return ctx->cfg_ptr->ext_ ## ext ; \
- }
-
-MATERIALISE_EXT_PREDICATE(XVentanaCondOps);
-
#ifdef TARGET_RISCV32
#define get_xl(ctx) MXL_RV32
#elif defined(CONFIG_USER_ONLY)
@@ -1106,7 +1083,7 @@ static void decode_opc(CPURISCVState *env, DisasContext
*ctx, uint16_t opcode)
* that are tested in-order until a decoder matches onto the opcode.
*/
static const struct {
- bool (*guard_func)(DisasContext *);
+ bool (*guard_func)(const RISCVCPUConfig *);
bool (*decode_func)(DisasContext *, uint32_t);
} decoders[] = {
{ always_true_p, decode_insn32 },
@@ -1135,7 +1112,7 @@ static void decode_opc(CPURISCVState *env, DisasContext
*ctx, uint16_t opcode)
ctx->pc_succ_insn = ctx->base.pc_next + 4;
for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
- if (decoders[i].guard_func(ctx) &&
+ if (decoders[i].guard_func(ctx->cfg_ptr) &&
decoders[i].decode_func(ctx, opcode32)) {
return;
}