[PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1

[Weiwei Li]

Currently, we use the current env->xl as the xlen for address. However, the 
xlen for data address should be changed to the xlen related to MPP when MPRV=1.

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-addr-xl-upstream

Weiwei Li (2):
  target/riscv: Add additional xlen for address when MPRV=1
  target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV

 target/riscv/cpu.h        | 49 +++++++++++++++++++++++++++++++++------
 target/riscv/cpu_helper.c |  8 +++++--
 target/riscv/csr.c        | 27 +++++++++++++++------
 target/riscv/translate.c  | 13 ++++++++++-
 4 files changed, 80 insertions(+), 17 deletions(-)

-- 
2.25.1