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Re: [PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1
From: |
Alistair Francis |
Subject: |
Re: [PATCH 0/2] target/riscv: Fix the xlen for data address when MPRV=1 |
Date: |
Fri, 23 Jun 2023 12:22:35 +1000 |
On Wed, Jun 14, 2023 at 1:27 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> Currently, we use the current env->xl as the xlen for address. However, the
> xlen for data address should be changed to the xlen related to MPP when
> MPRV=1.
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-addr-xl-upstream
>
> Weiwei Li (2):
> target/riscv: Add additional xlen for address when MPRV=1
> target/riscv: update cur_pmbase/pmmask based on mode affected by MPRV
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.h | 49 +++++++++++++++++++++++++++++++++------
> target/riscv/cpu_helper.c | 8 +++++--
> target/riscv/csr.c | 27 +++++++++++++++------
> target/riscv/translate.c | 13 ++++++++++-
> 4 files changed, 80 insertions(+), 17 deletions(-)
>
> --
> 2.25.1
>
>