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[PATCH v3 8/8] target/tricore: Add DISABLE insn variant
From: |
Bastian Koppelmann |
Subject: |
[PATCH v3 8/8] target/tricore: Add DISABLE insn variant |
Date: |
Wed, 14 Jun 2023 12:00:39 +0200 |
this variant saves the 'IE' bit to a 'd' register. The 'IE' bitfield
changed from ISA version 1.6.1, so we add icr_ie_offset to DisasContext
as with the other DISABLE insn.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 11 ++++++++++-
target/tricore/tricore-opcodes.h | 1 +
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index f01000efd4..6712d98f6e 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -75,7 +75,7 @@ typedef struct DisasContext {
int mem_idx;
uint32_t hflags, saved_hflags;
uint64_t features;
- uint32_t icr_ie_mask;
+ uint32_t icr_ie_mask, icr_ie_offset;
} DisasContext;
static int has_feature(DisasContext *ctx, int feature)
@@ -7883,6 +7883,13 @@ static void decode_sys_interrupts(DisasContext *ctx)
case OPC2_32_SYS_DISABLE:
tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
break;
+ case OPC2_32_SYS_DISABLE_D:
+ if (has_feature(ctx, TRICORE_FEATURE_16)) {
+ tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR, ctx->icr_ie_offset, 1);
+ tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ } else {
+ generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
+ }
case OPC2_32_SYS_DSYNC:
break;
case OPC2_32_SYS_ENABLE:
@@ -8302,8 +8309,10 @@ static void
tricore_tr_init_disas_context(DisasContextBase *dcbase,
ctx->features = env->features;
if (has_feature(ctx, TRICORE_FEATURE_161)) {
ctx->icr_ie_mask = R_ICR_IE_161_MASK;
+ ctx->icr_ie_offset = R_ICR_IE_161_SHIFT;
} else {
ctx->icr_ie_mask = R_ICR_IE_13_MASK;
+ ctx->icr_ie_offset = R_ICR_IE_13_SHIFT;
}
}
diff --git a/target/tricore/tricore-opcodes.h b/target/tricore/tricore-opcodes.h
index af63926731..bc62b73173 100644
--- a/target/tricore/tricore-opcodes.h
+++ b/target/tricore/tricore-opcodes.h
@@ -1467,6 +1467,7 @@ enum {
enum {
OPC2_32_SYS_DEBUG = 0x04,
OPC2_32_SYS_DISABLE = 0x0d,
+ OPC2_32_SYS_DISABLE_D = 0x0f, /* 1.6 up */
OPC2_32_SYS_DSYNC = 0x12,
OPC2_32_SYS_ENABLE = 0x0c,
OPC2_32_SYS_ISYNC = 0x13,
--
2.40.1
- [PATCH v3 0/8] TriCore 1.6.2 Instructions, Bastian Koppelmann, 2023/06/14
- [PATCH v3 1/8] target/tricore: Introduce ISA 1.6.2 feature, Bastian Koppelmann, 2023/06/14
- [PATCH v3 2/8] target/tricore: Add popcnt.w insn, Bastian Koppelmann, 2023/06/14
- [PATCH v3 3/8] target/tricore: Add LHA insn, Bastian Koppelmann, 2023/06/14
- [PATCH v3 4/8] target/tricore: Add crc32l.w insn, Bastian Koppelmann, 2023/06/14
- [PATCH v3 5/8] target/tricore: Add crc32.b insn, Bastian Koppelmann, 2023/06/14
- [PATCH v3 6/8] target/tricore: Add shuffle insn, Bastian Koppelmann, 2023/06/14
- [PATCH v3 7/8] target/tricore: Implement SYCSCALL insn, Bastian Koppelmann, 2023/06/14
- [PATCH v3 8/8] target/tricore: Add DISABLE insn variant,
Bastian Koppelmann <=