so we can recognize exceptions after re-enabling interrupts.
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
target/tricore/translate.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index d4f7415158..6164ba6539 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -38,6 +38,7 @@
#undef HELPER_H
#define DISAS_EXIT DISAS_TARGET_0
+#define DISAS_EXIT_UPDATE DISAS_TARGET_1
/*
* TCG registers
@@ -7880,11 +7881,13 @@ static void decode_sys_interrupts(DisasContext *ctx)
break;
case OPC2_32_SYS_DISABLE:
tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
break;
case OPC2_32_SYS_DISABLE_D:
if (has_feature(ctx, TRICORE_FEATURE_16)) {
tcg_gen_extract_tl(cpu_gpr_d[r1], cpu_ICR, ctx->icr_ie_offset, 1);
tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~ctx->icr_ie_mask);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
} else {
generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
}
@@ -7892,6 +7895,7 @@ static void decode_sys_interrupts(DisasContext *ctx)
break;
case OPC2_32_SYS_ENABLE:
tcg_gen_ori_tl(cpu_ICR, cpu_ICR, ctx->icr_ie_mask);
+ ctx->base.is_jmp = DISAS_EXIT_UPDATE;
break;
case OPC2_32_SYS_ISYNC:
break;
@@ -8379,6 +8383,9 @@ static void tricore_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cpu)
case DISAS_TOO_MANY:
gen_goto_tb(ctx, 0, ctx->base.pc_next);
break;
+ case DISAS_EXIT_UPDATE:
+ gen_save_pc(ctx->base.pc_next);
+ /* fall through */
case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0);
break;