Re: [PATCH v2 7/8] target/tricore: Honour privilege changes on PSW write

[Richard Henderson]

On 6/16/23 17:28, Bastian Koppelmann wrote:
> the CPU can change the privilege level by writing the corresponding bits
> in PSW. If this happens all instructions after this 'mtcr' in the TB are
> translated with the wrong privilege level. So we have to exit to the
> cpu_loop() and start translating again with the new privilege level.
>
> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> ---
> v1 -> v2:
>      - Removed helper_psw_write() calling cpu_loop_exit().
>        Instead we unconditionally exit for each write to psw.
>
>
>   target/tricore/translate.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
> diff --git a/target/tricore/translate.c b/target/tricore/translate.c
> index 71e3842601..5f9bc2b558 100644
> --- a/target/tricore/translate.c
> +++ b/target/tricore/translate.c
> @@ -333,7 +333,6 @@ static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
>       tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
>   }
>   
> -
>   /* We generate loads and store to core special function register (csfr) 
> through
>      the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
>      makros R, A and E, which allow read-only, all and endinit protected access.
> @@ -381,6 +380,7 @@ static inline void gen_mtcr(DisasContext *ctx, TCGv r1,
>           /* since we're caching PSW make this a special case */
>           if (offset == 0xfe04) {
>               gen_helper_psw_write(cpu_env, r1);
> +            ctx->base.is_jmp = DISAS_EXIT_UPDATE;
>           } else {
>               switch (offset) {
>   #include "csfr.h.inc"