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From: | Song Gao |
Subject: | Re: [PATCH v1 04/46] target/loongarch: Implement xvadd/xvsub |
Date: | Wed, 21 Jun 2023 17:56:51 +0800 |
User-agent: | Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 |
在 2023/6/21 下午5:27, Richard Henderson 写道:
On 6/21/23 11:19, Song Gao wrote:在 2023/6/20 下午8:25, Richard Henderson 写道:On 6/20/23 11:37, Song Gao wrote:+static bool gvec_xxx(DisasContext *ctx, arg_xxx *a, MemOp mop, + void (*func)(unsigned, uint32_t, uint32_t, + uint32_t, uint32_t, uint32_t)) +{ + uint32_t xd_ofs, xj_ofs, xk_ofs; + + CHECK_ASXE; + + xd_ofs = vec_full_offset(a->xd); + xj_ofs = vec_full_offset(a->xj); + xk_ofs = vec_full_offset(a->xk); + + func(mop, xd_ofs, xj_ofs, xk_ofs, 32, ctx->vl / 8); + return true; +}Comparing gvec_xxx vs gvec_vvv for LSX,func(mop, vd_ofs, vj_ofs, vk_ofs, 16, ctx->vl/8);gvec_vvv will write 16 bytes of output, followed by 16 bytes of zero to satisfy vl / 8.I presume this is the intended behaviour of mixing LSX with LASX, that the high 128-bits that are not considered by the LSX instruction are zeroed on write?Yes, the LSX instruction can ignore the high 128-bits.Ignore != write zeros on output. What is the behaviour?
Unpredictable, For more, LSX:LA64 fp instructiosn change fp registers value, the same num LSX registers [127: 64] is unpredictable.
LASX:LA64 fp instructions change fp_registers value, the same num LASX registers[255: 64] is unpredictable. LSX instructions change LSX registers value, the same num LASX registers[255: 128] is Unpredictable.
Thanks. Song Gao.
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