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[PATCH v4 00/17] Add RISC-V vector cryptographic instruction set support
From: |
Max Chou |
Subject: |
[PATCH v4 00/17] Add RISC-V vector cryptographic instruction set support |
Date: |
Fri, 23 Jun 2023 00:16:16 +0800 |
This patchset provides an implementation for Zvbb, Zvbc, Zvkned, Zvknh, Zvksh,
Zvkg, and Zvksed of the draft RISC-V vector cryptography extensions as per the
v20230620 version of the specification(1) (168e7b4).
This is an update to the patchset submitted to qemu-devel on Thu, 22 Jun 2023
05:49:20 -0700,
v2:
squashed commits into one commit per extension with separate commits for
each refactoring
unified trans_rvzvk*.c.inc files into one trans_rvvk.c.inc
style fixes in insn32.decode and other files
added macros for EGS values in translation functions.
updated from v20230303 to v20230407 of the spec:
Zvkb has been split into Zvbb and Zvbc
vbrev, vclz, vctz, vcpop and vwsll have been added to Zvbb.
v3:
New patch 03/19 removes redundant “cpu_vl == 0” checks from trans_rvv.c.inc
Introduction of new tcg ops has been factored out of patch 11/19 and into
09/19
These ops are now added to non riscv-specific files
v4:
New patch 08/17 fixes the tcg_gen_gvec_andcs temporary variable issue
Patch 09/17 fixes imm mode for vror.vi
Rebased to riscv-to-apply.next branch (de395bb):
Replace vstart constraint checking by TCG op
Verified by code examples provided by vector crypto spec repository
(riscv-crypto)
As v20230620 is a frozen version, we are not expecting any significant changes
to the specification or this patch series.
Please note that the Zvkt data-independent execution latency extension (and all
extensions including it) has not been implemented, and we would recommend not
using these patches in an environment where timing attacks are an issue.
Work performed by Dickon, Lawrence, Nazar, Kiran, and William from Codethink
sponsored by SiFive, as well as Max Chou and Frank Chang from SiFive.
https://github.com/riscv/riscv-crypto/releases
Thanks to those who have already reviewed:
Weiwei Li liweiwei@iscas.ac.cn
[PATCH v3 01/19] target/riscv: Refactor some of the generic vector
functionality
[PATCH v3 02/19] target/riscv: Refactor vector-vector translation macro
[PATCH v3 03/19] target/riscv: Remove redundant "cpu_vl == 0" checks
[PATCH v3 05/19] target/riscv: Move vector translation checks
[PATCH v3 06/19] target/riscv: Refactor translation of vector-widening
instruction
[PATCH v3 07/19] target/riscv: Refactor some of the generic vector
functionality
[PATCH v3 19/19] target/riscv: Expose Zvk* and Zvb[b, c] cpu properties
Richard Henderson richard.henderson@linaro.org
[PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro
[PATCH v2 04/17] target/riscv: Move vector translation checks
[PATCH v2 05/17] target/riscv: Refactor translation of vector-widening
instruction
[PATCH v2 07/17] qemu/bitops.h: Limit rotate amounts
[PATCH v2 08/17] qemu/host-utils.h: Add clz and ctz functions for
lower-bit integers
[PATCH v2 14/17] crypto: Create sm4_subword
Alistair Francis alistair.francis@wdc.com
[PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro
Philipp Tomsich philipp.tomsich@vrull.eu
Various v1 reviews
Christoph Müllner christoph.muellner@vrull.eu
Various v1 reviews
Dickon Hood (2):
target/riscv: Refactor translation of vector-widening instruction
target/riscv: Add Zvbb ISA extension support
Kiran Ostrolenk (4):
target/riscv: Refactor some of the generic vector functionality
target/riscv: Refactor vector-vector translation macro
target/riscv: Refactor some of the generic vector functionality
target/riscv: Add Zvknh ISA extension support
Lawrence Hunter (2):
target/riscv: Add Zvbc ISA extension support
target/riscv: Add Zvksh ISA extension support
Max Chou (4):
tcg: Fix temporary variable in tcg_gen_gvec_andcs
crypto: Create sm4_subword
crypto: Add SM4 constant parameter CK
target/riscv: Add Zvksed ISA extension support
Nazar Kazakov (5):
target/riscv: Remove redundant "cpu_vl == 0" checks
target/riscv: Move vector translation checks
target/riscv: Add Zvkned ISA extension support
target/riscv: Add Zvkg ISA extension support
target/riscv: Expose Zvk* and Zvb[b,c] cpu properties
crypto/sm4.c | 10 +
include/crypto/sm4.h | 9 +
target/arm/tcg/crypto_helper.c | 10 +-
target/riscv/cpu.c | 37 +
target/riscv/cpu_cfg.h | 8 +
target/riscv/helper.h | 95 ++
target/riscv/insn32.decode | 58 ++
target/riscv/insn_trans/trans_rvv.c.inc | 171 ++--
target/riscv/insn_trans/trans_rvvk.c.inc | 585 ++++++++++++
target/riscv/meson.build | 4 +-
target/riscv/op_helper.c | 6 +
target/riscv/translate.c | 1 +
target/riscv/vcrypto_helper.c | 1052 ++++++++++++++++++++++
target/riscv/vector_helper.c | 243 +----
target/riscv/vector_internals.c | 81 ++
target/riscv/vector_internals.h | 228 +++++
tcg/tcg-op-gvec.c | 2 +-
17 files changed, 2244 insertions(+), 356 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc
create mode 100644 target/riscv/vcrypto_helper.c
create mode 100644 target/riscv/vector_internals.c
create mode 100644 target/riscv/vector_internals.h
--
2.31.1
- [PATCH v4 00/17] Add RISC-V vector cryptographic instruction set support,
Max Chou <=
- [PATCH v4 01/17] target/riscv: Refactor some of the generic vector functionality, Max Chou, 2023/06/22
- [PATCH v4 02/17] target/riscv: Refactor vector-vector translation macro, Max Chou, 2023/06/22
- [PATCH v4 03/17] target/riscv: Remove redundant "cpu_vl == 0" checks, Max Chou, 2023/06/22
- [PATCH v4 04/17] target/riscv: Add Zvbc ISA extension support, Max Chou, 2023/06/22
- [PATCH v4 06/17] target/riscv: Refactor translation of vector-widening instruction, Max Chou, 2023/06/22
- [PATCH v4 05/17] target/riscv: Move vector translation checks, Max Chou, 2023/06/22
- [PATCH v4 07/17] target/riscv: Refactor some of the generic vector functionality, Max Chou, 2023/06/22
- [PATCH v4 08/17] tcg: Fix temporary variable in tcg_gen_gvec_andcs, Max Chou, 2023/06/22