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[PATCH v4 08/17] tcg: Fix temporary variable in tcg_gen_gvec_andcs
From: |
Max Chou |
Subject: |
[PATCH v4 08/17] tcg: Fix temporary variable in tcg_gen_gvec_andcs |
Date: |
Fri, 23 Jun 2023 00:16:24 +0800 |
The 5th parameter of tcg_gen_gvec_2s should be replaces by the temporary
tmp variable in the tcg_gen_gvec_andcs function.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
tcg/tcg-op-gvec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 95a588d6d2..a062239804 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -2774,7 +2774,7 @@ void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs,
uint32_t aofs,
TCGv_i64 tmp = tcg_temp_ebb_new_i64();
tcg_gen_dup_i64(vece, tmp, c);
- tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g);
+ tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &g);
tcg_temp_free_i64(tmp);
}
--
2.31.1
- [PATCH v4 00/17] Add RISC-V vector cryptographic instruction set support, Max Chou, 2023/06/22
- [PATCH v4 01/17] target/riscv: Refactor some of the generic vector functionality, Max Chou, 2023/06/22
- [PATCH v4 02/17] target/riscv: Refactor vector-vector translation macro, Max Chou, 2023/06/22
- [PATCH v4 03/17] target/riscv: Remove redundant "cpu_vl == 0" checks, Max Chou, 2023/06/22
- [PATCH v4 04/17] target/riscv: Add Zvbc ISA extension support, Max Chou, 2023/06/22
- [PATCH v4 06/17] target/riscv: Refactor translation of vector-widening instruction, Max Chou, 2023/06/22
- [PATCH v4 05/17] target/riscv: Move vector translation checks, Max Chou, 2023/06/22
- [PATCH v4 07/17] target/riscv: Refactor some of the generic vector functionality, Max Chou, 2023/06/22
- [PATCH v4 08/17] tcg: Fix temporary variable in tcg_gen_gvec_andcs,
Max Chou <=
- [PATCH v4 09/17] target/riscv: Add Zvbb ISA extension support, Max Chou, 2023/06/22
- [PATCH v4 10/17] target/riscv: Add Zvkned ISA extension support, Max Chou, 2023/06/22
- [PATCH v4 11/17] target/riscv: Add Zvknh ISA extension support, Max Chou, 2023/06/22