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[PULL 14/30] target/ppc: Fix instruction loading endianness in alignment
From: |
Cédric Le Goater |
Subject: |
[PULL 14/30] target/ppc: Fix instruction loading endianness in alignment interrupt |
Date: |
Mon, 26 Jun 2023 07:56:31 +0200 |
From: Nicholas Piggin <npiggin@gmail.com>
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/excp_helper.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 12d8a7257b29..a2801f6e6b6a 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -133,6 +133,26 @@ static void dump_hcall(CPUPPCState *env)
env->nip);
}
+#ifdef CONFIG_TCG
+/* Return true iff byteswap is needed to load instruction */
+static inline bool insn_need_byteswap(CPUArchState *env)
+{
+ /* SYSTEM builds TARGET_BIG_ENDIAN. Need to swap when MSR[LE] is set */
+ return !!(env->msr & ((target_ulong)1 << MSR_LE));
+}
+
+static uint32_t ppc_ldl_code(CPUArchState *env, hwaddr addr)
+{
+ uint32_t insn = cpu_ldl_code(env, addr);
+
+ if (insn_need_byteswap(env)) {
+ insn = bswap32(insn);
+ }
+
+ return insn;
+}
+#endif
+
static void ppc_excp_debug_sw_tlb(CPUPPCState *env, int excp)
{
const char *es;
@@ -3104,7 +3124,7 @@ void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr
vaddr,
/* Restore state and reload the insn we executed, for filling in DSISR. */
cpu_restore_state(cs, retaddr);
- insn = cpu_ldl_code(env, env->nip);
+ insn = ppc_ldl_code(env, env->nip);
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_4xx:
--
2.41.0
- [PULL 04/30] MAINTAINERS: Add reviewer for PowerPC TCG CPUs, (continued)
- [PULL 04/30] MAINTAINERS: Add reviewer for PowerPC TCG CPUs, Cédric Le Goater, 2023/06/26
- [PULL 06/30] ppc/prep: Report an error when run with KVM, Cédric Le Goater, 2023/06/26
- [PULL 05/30] MAINTAINERS: Add reviewer for XIVE, Cédric Le Goater, 2023/06/26
- [PULL 07/30] ppc/bamboo: Report an error when run with KVM, Cédric Le Goater, 2023/06/26
- [PULL 09/30] target/ppc: Fix timer register accessors when !KVM, Cédric Le Goater, 2023/06/26
- [PULL 08/30] ppc/pnv: Rephrase error when run with KVM, Cédric Le Goater, 2023/06/26
- [PULL 12/30] ppc/spapr: load and store l2 state with helper functions, Cédric Le Goater, 2023/06/26
- [PULL 17/30] target/ppc: Implement HEIR SPR, Cédric Le Goater, 2023/06/26
- [PULL 10/30] ppc/spapr: H_ENTER_NESTED should restore host XER ca field, Cédric Le Goater, 2023/06/26
- [PULL 13/30] ppc/spapr: Move spapr nested HV to a new file, Cédric Le Goater, 2023/06/26
- [PULL 14/30] target/ppc: Fix instruction loading endianness in alignment interrupt,
Cédric Le Goater <=
- [PULL 11/30] ppc/spapr: Add a nested state struct, Cédric Le Goater, 2023/06/26
- [PULL 16/30] target/ppc: Add SRR1 prefix indication to interrupt handlers, Cédric Le Goater, 2023/06/26
- [PULL 18/30] target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts, Cédric Le Goater, 2023/06/26
- [PULL 15/30] target/ppc: Change partition-scope translate interface, Cédric Le Goater, 2023/06/26
- [PULL 19/30] target/ppc: Better CTRL SPR implementation, Cédric Le Goater, 2023/06/26
- [PULL 22/30] target/ppc: Add support for SMT CTRL register, Cédric Le Goater, 2023/06/26
- [PULL 23/30] target/ppc: Add msgsnd/p and DPDES SMT support, Cédric Le Goater, 2023/06/26
- [PULL 26/30] tests/avocado: boot ppc64 pseries to Linux VFS mount, Cédric Le Goater, 2023/06/26
- [PULL 30/30] tests/avocado: ppc test VOF bios Linux boot, Cédric Le Goater, 2023/06/26
- [PULL 20/30] target/ppc: Fix sc instruction handling of LEV field, Cédric Le Goater, 2023/06/26