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[PULL 20/30] target/ppc: Fix sc instruction handling of LEV field
From: |
Cédric Le Goater |
Subject: |
[PULL 20/30] target/ppc: Fix sc instruction handling of LEV field |
Date: |
Mon, 26 Jun 2023 07:56:37 +0200 |
From: Nicholas Piggin <npiggin@gmail.com>
The top bits of the LEV field of the sc instruction are to be treated as
as a reserved field rather than a reserved value, meaning LEV is
effectively the bottom bit. LEV=0xF should be treated as LEV=1 and be
a hypercall, for example.
This changes the instruction execution to just set lev from the low bit
of the field. Processors which don't support the LEV field will continue
to ignore it.
ISA v3.1 defines LEV to be 2 bits, in order to add the 'sc 2' ultracall
instruction. TCG does not support Ultravisor, so don't worry about
that bit.
Suggested-by: "Harsh Prateek Bora" <harshpb@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/translate.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 1ade06361679..8f74a864e48e 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -4429,7 +4429,12 @@ static void gen_sc(DisasContext *ctx)
{
uint32_t lev;
- lev = (ctx->opcode >> 5) & 0x7F;
+ /*
+ * LEV is a 7-bit field, but the top 6 bits are treated as a reserved
+ * field (i.e., ignored). ISA v3.1 changes that to 5 bits, but that is
+ * for Ultravisor which TCG does not support, so just ignore the top 6.
+ */
+ lev = (ctx->opcode >> 5) & 0x1;
gen_exception_err(ctx, POWERPC_SYSCALL, lev);
}
--
2.41.0
- [PULL 14/30] target/ppc: Fix instruction loading endianness in alignment interrupt, (continued)
- [PULL 14/30] target/ppc: Fix instruction loading endianness in alignment interrupt, Cédric Le Goater, 2023/06/26
- [PULL 11/30] ppc/spapr: Add a nested state struct, Cédric Le Goater, 2023/06/26
- [PULL 16/30] target/ppc: Add SRR1 prefix indication to interrupt handlers, Cédric Le Goater, 2023/06/26
- [PULL 18/30] target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts, Cédric Le Goater, 2023/06/26
- [PULL 15/30] target/ppc: Change partition-scope translate interface, Cédric Le Goater, 2023/06/26
- [PULL 19/30] target/ppc: Better CTRL SPR implementation, Cédric Le Goater, 2023/06/26
- [PULL 22/30] target/ppc: Add support for SMT CTRL register, Cédric Le Goater, 2023/06/26
- [PULL 23/30] target/ppc: Add msgsnd/p and DPDES SMT support, Cédric Le Goater, 2023/06/26
- [PULL 26/30] tests/avocado: boot ppc64 pseries to Linux VFS mount, Cédric Le Goater, 2023/06/26
- [PULL 30/30] tests/avocado: ppc test VOF bios Linux boot, Cédric Le Goater, 2023/06/26
- [PULL 20/30] target/ppc: Fix sc instruction handling of LEV field,
Cédric Le Goater <=
- [PULL 29/30] pnv/xive2: Check TIMA special ops against a dedicated array for P10, Cédric Le Goater, 2023/06/26
- [PULL 28/30] pnv/xive2: Add a get_config() method on the presenter class, Cédric Le Goater, 2023/06/26
- [PULL 27/30] tests/avocado: Add ppc64 pseries multiprocessor boot tests, Cédric Le Goater, 2023/06/26
- [PULL 21/30] target/ppc: Add initial flags and helpers for SMT support, Cédric Le Goater, 2023/06/26
- [PULL 24/30] hw/ppc/spapr: Test whether TCG is enabled with tcg_enabled(), Cédric Le Goater, 2023/06/26
- [PULL 25/30] spapr: TCG allow up to 8-thread SMT on POWER8 and newer CPUs, Cédric Le Goater, 2023/06/26
- Re: [PULL 00/30] ppc queue, Richard Henderson, 2023/06/26