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[PULL 07/22] accel/tcg: Widen pc to vaddr in CPUJumpCache
From: |
Richard Henderson |
Subject: |
[PULL 07/22] accel/tcg: Widen pc to vaddr in CPUJumpCache |
Date: |
Mon, 26 Jun 2023 17:39:30 +0200 |
From: Anton Johansson <anjo@rev.ng>
Related functions dealing with the jump cache are also updated.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-8-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/tb-hash.h | 12 ++++++------
accel/tcg/tb-jmp-cache.h | 2 +-
accel/tcg/cputlb.c | 2 +-
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h
index 2ba2193731..a0c61f25cd 100644
--- a/accel/tcg/tb-hash.h
+++ b/accel/tcg/tb-hash.h
@@ -35,16 +35,16 @@
#define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1)
#define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE)
-static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
+static inline unsigned int tb_jmp_cache_hash_page(vaddr pc)
{
- target_ulong tmp;
+ vaddr tmp;
tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
}
-static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
+static inline unsigned int tb_jmp_cache_hash_func(vaddr pc)
{
- target_ulong tmp;
+ vaddr tmp;
tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
| (tmp & TB_JMP_ADDR_MASK));
@@ -53,7 +53,7 @@ static inline unsigned int
tb_jmp_cache_hash_func(target_ulong pc)
#else
/* In user-mode we can get better hashing because we do not have a TLB */
-static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
+static inline unsigned int tb_jmp_cache_hash_func(vaddr pc)
{
return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1);
}
@@ -61,7 +61,7 @@ static inline unsigned int
tb_jmp_cache_hash_func(target_ulong pc)
#endif /* CONFIG_SOFTMMU */
static inline
-uint32_t tb_hash_func(tb_page_addr_t phys_pc, target_ulong pc,
+uint32_t tb_hash_func(tb_page_addr_t phys_pc, vaddr pc,
uint32_t flags, uint64_t flags2, uint32_t cf_mask)
{
return qemu_xxhash8(phys_pc, pc, flags2, flags, cf_mask);
diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h
index bee87eb840..bb424c8a05 100644
--- a/accel/tcg/tb-jmp-cache.h
+++ b/accel/tcg/tb-jmp-cache.h
@@ -21,7 +21,7 @@ struct CPUJumpCache {
struct rcu_head rcu;
struct {
TranslationBlock *tb;
- target_ulong pc;
+ vaddr pc;
} array[TB_JMP_CACHE_SIZE];
};
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index cc53d0fb64..bdf400f6e6 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -99,7 +99,7 @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
desc->window_max_entries = max_entries;
}
-static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr)
+static void tb_jmp_cache_clear_page(CPUState *cpu, vaddr page_addr)
{
CPUJumpCache *jc = cpu->tb_jmp_cache;
int i, i0;
--
2.34.1
- [PULL 00/22] tcg patch queue, Richard Henderson, 2023/06/26
- [PULL 07/22] accel/tcg: Widen pc to vaddr in CPUJumpCache,
Richard Henderson <=
- [PULL 05/22] accel/tcg/cputlb.c: Widen addr in MMULookupPageData, Richard Henderson, 2023/06/26
- [PULL 08/22] accel: Replace target_ulong with vaddr in probe_*(), Richard Henderson, 2023/06/26
- [PULL 02/22] accel/tcg/translate-all.c: Widen pc and cs_base, Richard Henderson, 2023/06/26
- [PULL 03/22] target: Widen pc/cs_base in cpu_get_tb_cpu_state, Richard Henderson, 2023/06/26
- [PULL 09/22] accel/tcg: Replace target_ulong with vaddr in *_mmu_lookup(), Richard Henderson, 2023/06/26
- [PULL 04/22] accel/tcg/cputlb.c: Widen CPUTLBEntry access functions, Richard Henderson, 2023/06/26
- [PULL 06/22] accel/tcg/cpu-exec.c: Widen pc to vaddr, Richard Henderson, 2023/06/26
- [PULL 01/22] accel: Replace target_ulong in tlb_*(), Richard Henderson, 2023/06/26
- [PULL 18/22] tcg: Add host memory barriers to cpu_ldst.h interfaces, Richard Henderson, 2023/06/26
- [PULL 21/22] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK, Richard Henderson, 2023/06/26