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[PULL 21/22] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK
From: |
Richard Henderson |
Subject: |
[PULL 21/22] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK |
Date: |
Mon, 26 Jun 2023 17:39:44 +0200 |
This frees up one bit of the primary tlb flags without
impacting the TLB_NOTDIRTY logic.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 8 ++++----
accel/tcg/cputlb.c | 18 ++++++++++++++----
2 files changed, 18 insertions(+), 8 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 4422f4bb07..b5618613cc 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -325,8 +325,6 @@ CPUArchState *cpu_copy(CPUArchState *env);
#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
/* Set if TLB entry is an IO callback. */
#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
-/* Set if TLB entry contains a watchpoint. */
-#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4))
/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5))
/* Set if TLB entry writes ignored. */
@@ -338,7 +336,7 @@ CPUArchState *cpu_copy(CPUArchState *env);
*/
#define TLB_FLAGS_MASK \
(TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
- | TLB_WATCHPOINT | TLB_FORCE_SLOW | TLB_DISCARD_WRITE)
+ | TLB_FORCE_SLOW | TLB_DISCARD_WRITE)
/*
* Flags stored in CPUTLBEntryFull.slow_flags[x].
@@ -346,8 +344,10 @@ CPUArchState *cpu_copy(CPUArchState *env);
*/
/* Set if TLB entry requires byte swap. */
#define TLB_BSWAP (1 << 0)
+/* Set if TLB entry contains a watchpoint. */
+#define TLB_WATCHPOINT (1 << 1)
-#define TLB_SLOW_FLAGS_MASK TLB_BSWAP
+#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT)
/* The two sets of flags must not overlap. */
QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 3671846744..5b51eff5a4 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1981,7 +1981,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, vaddr
addr, MemOpIdx oi,
*/
goto stop_the_world;
}
- /* Collect TLB_WATCHPOINT for read. */
+ /* Collect tlb flags for read. */
tlb_addr |= tlbe->addr_read;
/* Notice an IO access or a needs-MMU-lookup access */
@@ -1998,9 +1998,19 @@ static void *atomic_mmu_lookup(CPUArchState *env, vaddr
addr, MemOpIdx oi,
notdirty_write(env_cpu(env), addr, size, full, retaddr);
}
- if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
- cpu_check_watchpoint(env_cpu(env), addr, size, full->attrs,
- BP_MEM_READ | BP_MEM_WRITE, retaddr);
+ if (unlikely(tlb_addr & TLB_FORCE_SLOW)) {
+ int wp_flags = 0;
+
+ if (full->slow_flags[MMU_DATA_STORE] & TLB_WATCHPOINT) {
+ wp_flags |= BP_MEM_WRITE;
+ }
+ if (full->slow_flags[MMU_DATA_LOAD] & TLB_WATCHPOINT) {
+ wp_flags |= BP_MEM_READ;
+ }
+ if (wp_flags) {
+ cpu_check_watchpoint(env_cpu(env), addr, size,
+ full->attrs, wp_flags, retaddr);
+ }
}
return hostaddr;
--
2.34.1
- [PULL 07/22] accel/tcg: Widen pc to vaddr in CPUJumpCache, (continued)
- [PULL 07/22] accel/tcg: Widen pc to vaddr in CPUJumpCache, Richard Henderson, 2023/06/26
- [PULL 05/22] accel/tcg/cputlb.c: Widen addr in MMULookupPageData, Richard Henderson, 2023/06/26
- [PULL 08/22] accel: Replace target_ulong with vaddr in probe_*(), Richard Henderson, 2023/06/26
- [PULL 02/22] accel/tcg/translate-all.c: Widen pc and cs_base, Richard Henderson, 2023/06/26
- [PULL 03/22] target: Widen pc/cs_base in cpu_get_tb_cpu_state, Richard Henderson, 2023/06/26
- [PULL 09/22] accel/tcg: Replace target_ulong with vaddr in *_mmu_lookup(), Richard Henderson, 2023/06/26
- [PULL 04/22] accel/tcg/cputlb.c: Widen CPUTLBEntry access functions, Richard Henderson, 2023/06/26
- [PULL 06/22] accel/tcg/cpu-exec.c: Widen pc to vaddr, Richard Henderson, 2023/06/26
- [PULL 01/22] accel: Replace target_ulong in tlb_*(), Richard Henderson, 2023/06/26
- [PULL 18/22] tcg: Add host memory barriers to cpu_ldst.h interfaces, Richard Henderson, 2023/06/26
- [PULL 21/22] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK,
Richard Henderson <=
- [PULL 17/22] tcg: Do not elide memory barriers for !CF_PARALLEL in system mode, Richard Henderson, 2023/06/26
- [PULL 10/22] accel/tcg: Replace target_ulong with vaddr in translator_*(), Richard Henderson, 2023/06/26
- [PULL 20/22] accel/tcg: Store some tlb flags in CPUTLBEntryFull, Richard Henderson, 2023/06/26
- [PULL 11/22] cpu: Replace target_ulong with hwaddr in tb_invalidate_phys_addr(), Richard Henderson, 2023/06/26
- [PULL 12/22] softfloat: use QEMU_FLATTEN to avoid mistaken isra inlining, Richard Henderson, 2023/06/26
- [PULL 13/22] tests/plugin: Remove duplicate insn log from libinsn.so, Richard Henderson, 2023/06/26
- [PULL 16/22] target/microblaze: Define TCG_GUEST_DEFAULT_MO, Richard Henderson, 2023/06/26
- [PULL 15/22] tcg: Fix temporary variable in tcg_gen_gvec_andcs, Richard Henderson, 2023/06/26
- [PULL 22/22] accel/tcg: Renumber TLB_DISCARD_WRITE, Richard Henderson, 2023/06/26
- [PULL 19/22] accel/tcg: Remove check_tcg_memory_orders_compatible, Richard Henderson, 2023/06/26