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[PULL 22/22] accel/tcg: Renumber TLB_DISCARD_WRITE
From: |
Richard Henderson |
Subject: |
[PULL 22/22] accel/tcg: Renumber TLB_DISCARD_WRITE |
Date: |
Mon, 26 Jun 2023 17:39:45 +0200 |
Move to fill a hole in the set of bits.
Reduce the total number of tlb bits by 1.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 4 ++--
tcg/tcg-op-ldst.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index b5618613cc..8018ce783e 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -325,10 +325,10 @@ CPUArchState *cpu_copy(CPUArchState *env);
#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
/* Set if TLB entry is an IO callback. */
#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
+/* Set if TLB entry writes ignored. */
+#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4))
/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5))
-/* Set if TLB entry writes ignored. */
-#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6))
/*
* Use this mask to check interception with an alignment mask
diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c
index a4f51bfb6e..0fcc1618e5 100644
--- a/tcg/tcg-op-ldst.c
+++ b/tcg/tcg-op-ldst.c
@@ -39,7 +39,7 @@ static void check_max_alignment(unsigned a_bits)
* The requested alignment cannot overlap the TLB flags.
* FIXME: Must keep the count up-to-date with "exec/cpu-all.h".
*/
- tcg_debug_assert(a_bits + 6 <= tcg_ctx->page_bits);
+ tcg_debug_assert(a_bits + 5 <= tcg_ctx->page_bits);
#endif
}
--
2.34.1
- [PULL 18/22] tcg: Add host memory barriers to cpu_ldst.h interfaces, (continued)
- [PULL 18/22] tcg: Add host memory barriers to cpu_ldst.h interfaces, Richard Henderson, 2023/06/26
- [PULL 21/22] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK, Richard Henderson, 2023/06/26
- [PULL 17/22] tcg: Do not elide memory barriers for !CF_PARALLEL in system mode, Richard Henderson, 2023/06/26
- [PULL 10/22] accel/tcg: Replace target_ulong with vaddr in translator_*(), Richard Henderson, 2023/06/26
- [PULL 20/22] accel/tcg: Store some tlb flags in CPUTLBEntryFull, Richard Henderson, 2023/06/26
- [PULL 11/22] cpu: Replace target_ulong with hwaddr in tb_invalidate_phys_addr(), Richard Henderson, 2023/06/26
- [PULL 12/22] softfloat: use QEMU_FLATTEN to avoid mistaken isra inlining, Richard Henderson, 2023/06/26
- [PULL 13/22] tests/plugin: Remove duplicate insn log from libinsn.so, Richard Henderson, 2023/06/26
- [PULL 16/22] target/microblaze: Define TCG_GUEST_DEFAULT_MO, Richard Henderson, 2023/06/26
- [PULL 15/22] tcg: Fix temporary variable in tcg_gen_gvec_andcs, Richard Henderson, 2023/06/26
- [PULL 22/22] accel/tcg: Renumber TLB_DISCARD_WRITE,
Richard Henderson <=
- [PULL 19/22] accel/tcg: Remove check_tcg_memory_orders_compatible, Richard Henderson, 2023/06/26
- [PULL 14/22] accel/tcg: remove CONFIG_PROFILER, Richard Henderson, 2023/06/26
- Re: [PULL 00/22] tcg patch queue, Richard Henderson, 2023/06/26