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[PULL 17/22] tcg: Do not elide memory barriers for !CF_PARALLEL in syste
From: |
Richard Henderson |
Subject: |
[PULL 17/22] tcg: Do not elide memory barriers for !CF_PARALLEL in system mode |
Date: |
Mon, 26 Jun 2023 17:39:40 +0200 |
The virtio devices require proper memory ordering between
the vcpus and the iothreads.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/tcg-op.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index c07de5d9f8..7aadb37756 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -102,7 +102,19 @@ void tcg_gen_br(TCGLabel *l)
void tcg_gen_mb(TCGBar mb_type)
{
- if (tcg_ctx->gen_tb->cflags & CF_PARALLEL) {
+#ifdef CONFIG_USER_ONLY
+ bool parallel = tcg_ctx->gen_tb->cflags & CF_PARALLEL;
+#else
+ /*
+ * It is tempting to elide the barrier in a uniprocessor context.
+ * However, even with a single cpu we have i/o threads running in
+ * parallel, and lack of memory order can result in e.g. virtio
+ * queue entries being read incorrectly.
+ */
+ bool parallel = true;
+#endif
+
+ if (parallel) {
tcg_gen_op1(INDEX_op_mb, mb_type);
}
}
--
2.34.1
- [PULL 05/22] accel/tcg/cputlb.c: Widen addr in MMULookupPageData, (continued)
- [PULL 05/22] accel/tcg/cputlb.c: Widen addr in MMULookupPageData, Richard Henderson, 2023/06/26
- [PULL 08/22] accel: Replace target_ulong with vaddr in probe_*(), Richard Henderson, 2023/06/26
- [PULL 02/22] accel/tcg/translate-all.c: Widen pc and cs_base, Richard Henderson, 2023/06/26
- [PULL 03/22] target: Widen pc/cs_base in cpu_get_tb_cpu_state, Richard Henderson, 2023/06/26
- [PULL 09/22] accel/tcg: Replace target_ulong with vaddr in *_mmu_lookup(), Richard Henderson, 2023/06/26
- [PULL 04/22] accel/tcg/cputlb.c: Widen CPUTLBEntry access functions, Richard Henderson, 2023/06/26
- [PULL 06/22] accel/tcg/cpu-exec.c: Widen pc to vaddr, Richard Henderson, 2023/06/26
- [PULL 01/22] accel: Replace target_ulong in tlb_*(), Richard Henderson, 2023/06/26
- [PULL 18/22] tcg: Add host memory barriers to cpu_ldst.h interfaces, Richard Henderson, 2023/06/26
- [PULL 21/22] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK, Richard Henderson, 2023/06/26
- [PULL 17/22] tcg: Do not elide memory barriers for !CF_PARALLEL in system mode,
Richard Henderson <=
- [PULL 10/22] accel/tcg: Replace target_ulong with vaddr in translator_*(), Richard Henderson, 2023/06/26
- [PULL 20/22] accel/tcg: Store some tlb flags in CPUTLBEntryFull, Richard Henderson, 2023/06/26
- [PULL 11/22] cpu: Replace target_ulong with hwaddr in tb_invalidate_phys_addr(), Richard Henderson, 2023/06/26
- [PULL 12/22] softfloat: use QEMU_FLATTEN to avoid mistaken isra inlining, Richard Henderson, 2023/06/26
- [PULL 13/22] tests/plugin: Remove duplicate insn log from libinsn.so, Richard Henderson, 2023/06/26
- [PULL 16/22] target/microblaze: Define TCG_GUEST_DEFAULT_MO, Richard Henderson, 2023/06/26
- [PULL 15/22] tcg: Fix temporary variable in tcg_gen_gvec_andcs, Richard Henderson, 2023/06/26
- [PULL 22/22] accel/tcg: Renumber TLB_DISCARD_WRITE, Richard Henderson, 2023/06/26
- [PULL 19/22] accel/tcg: Remove check_tcg_memory_orders_compatible, Richard Henderson, 2023/06/26
- [PULL 14/22] accel/tcg: remove CONFIG_PROFILER, Richard Henderson, 2023/06/26