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[PULL 10/22] accel/tcg: Replace target_ulong with vaddr in translator_*(
From: |
Richard Henderson |
Subject: |
[PULL 10/22] accel/tcg: Replace target_ulong with vaddr in translator_*() |
Date: |
Mon, 26 Jun 2023 17:39:33 +0200 |
From: Anton Johansson <anjo@rev.ng>
Use vaddr for guest virtual address in translator_use_goto_tb() and
translator_loop().
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230621135633.1649-11-anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/translator.h | 6 +++---
accel/tcg/translator.c | 10 +++++-----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/include/exec/translator.h b/include/exec/translator.h
index 224ae14aa7..a53d3243d4 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -142,8 +142,8 @@ typedef struct TranslatorOps {
* - When too many instructions have been translated.
*/
void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc,
- const TranslatorOps *ops, DisasContextBase *db);
+ vaddr pc, void *host_pc, const TranslatorOps *ops,
+ DisasContextBase *db);
/**
* translator_use_goto_tb
@@ -153,7 +153,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb,
int *max_insns,
* Return true if goto_tb is allowed between the current TB
* and the destination PC.
*/
-bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
+bool translator_use_goto_tb(DisasContextBase *db, vaddr dest);
/**
* translator_io_start
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 918a455e73..0fd9efceba 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -117,7 +117,7 @@ static void gen_tb_end(const TranslationBlock *tb, uint32_t
cflags,
}
}
-bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest)
+bool translator_use_goto_tb(DisasContextBase *db, vaddr dest)
{
/* Suppress goto_tb if requested. */
if (tb_cflags(db->tb) & CF_NO_GOTO_TB) {
@@ -129,8 +129,8 @@ bool translator_use_goto_tb(DisasContextBase *db,
target_ulong dest)
}
void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc,
- const TranslatorOps *ops, DisasContextBase *db)
+ vaddr pc, void *host_pc, const TranslatorOps *ops,
+ DisasContextBase *db)
{
uint32_t cflags = tb_cflags(tb);
TCGOp *icount_start_insn;
@@ -235,10 +235,10 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb,
int *max_insns,
}
static void *translator_access(CPUArchState *env, DisasContextBase *db,
- target_ulong pc, size_t len)
+ vaddr pc, size_t len)
{
void *host;
- target_ulong base, end;
+ vaddr base, end;
TranslationBlock *tb;
tb = db->tb;
--
2.34.1
- [PULL 08/22] accel: Replace target_ulong with vaddr in probe_*(), (continued)
- [PULL 08/22] accel: Replace target_ulong with vaddr in probe_*(), Richard Henderson, 2023/06/26
- [PULL 02/22] accel/tcg/translate-all.c: Widen pc and cs_base, Richard Henderson, 2023/06/26
- [PULL 03/22] target: Widen pc/cs_base in cpu_get_tb_cpu_state, Richard Henderson, 2023/06/26
- [PULL 09/22] accel/tcg: Replace target_ulong with vaddr in *_mmu_lookup(), Richard Henderson, 2023/06/26
- [PULL 04/22] accel/tcg/cputlb.c: Widen CPUTLBEntry access functions, Richard Henderson, 2023/06/26
- [PULL 06/22] accel/tcg/cpu-exec.c: Widen pc to vaddr, Richard Henderson, 2023/06/26
- [PULL 01/22] accel: Replace target_ulong in tlb_*(), Richard Henderson, 2023/06/26
- [PULL 18/22] tcg: Add host memory barriers to cpu_ldst.h interfaces, Richard Henderson, 2023/06/26
- [PULL 21/22] accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASK, Richard Henderson, 2023/06/26
- [PULL 17/22] tcg: Do not elide memory barriers for !CF_PARALLEL in system mode, Richard Henderson, 2023/06/26
- [PULL 10/22] accel/tcg: Replace target_ulong with vaddr in translator_*(),
Richard Henderson <=
- [PULL 20/22] accel/tcg: Store some tlb flags in CPUTLBEntryFull, Richard Henderson, 2023/06/26
- [PULL 11/22] cpu: Replace target_ulong with hwaddr in tb_invalidate_phys_addr(), Richard Henderson, 2023/06/26
- [PULL 12/22] softfloat: use QEMU_FLATTEN to avoid mistaken isra inlining, Richard Henderson, 2023/06/26
- [PULL 13/22] tests/plugin: Remove duplicate insn log from libinsn.so, Richard Henderson, 2023/06/26
- [PULL 16/22] target/microblaze: Define TCG_GUEST_DEFAULT_MO, Richard Henderson, 2023/06/26
- [PULL 15/22] tcg: Fix temporary variable in tcg_gen_gvec_andcs, Richard Henderson, 2023/06/26
- [PULL 22/22] accel/tcg: Renumber TLB_DISCARD_WRITE, Richard Henderson, 2023/06/26
- [PULL 19/22] accel/tcg: Remove check_tcg_memory_orders_compatible, Richard Henderson, 2023/06/26
- [PULL 14/22] accel/tcg: remove CONFIG_PROFILER, Richard Henderson, 2023/06/26
- Re: [PULL 00/22] tcg patch queue, Richard Henderson, 2023/06/26