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[PATCH v2 12/46] target/loongarch: Implement xvabsd
From: |
Song Gao |
Subject: |
[PATCH v2 12/46] target/loongarch: Implement xvabsd |
Date: |
Fri, 30 Jun 2023 15:58:30 +0800 |
This patch includes:
- XVABSD.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/disas.c | 9 +++++++++
target/loongarch/insn_trans/trans_lasx.c.inc | 9 +++++++++
target/loongarch/insns.decode | 9 +++++++++
target/loongarch/vec.h | 2 ++
target/loongarch/vec_helper.c | 2 --
5 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 8296aafa98..d0b1de39b8 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1842,6 +1842,15 @@ INSN_LASX(xvavgr_hu, vvv)
INSN_LASX(xvavgr_wu, vvv)
INSN_LASX(xvavgr_du, vvv)
+INSN_LASX(xvabsd_b, vvv)
+INSN_LASX(xvabsd_h, vvv)
+INSN_LASX(xvabsd_w, vvv)
+INSN_LASX(xvabsd_d, vvv)
+INSN_LASX(xvabsd_bu, vvv)
+INSN_LASX(xvabsd_hu, vvv)
+INSN_LASX(xvabsd_wu, vvv)
+INSN_LASX(xvabsd_du, vvv)
+
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index ac4cade845..bd8ba6c7b6 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -157,6 +157,15 @@ TRANS(xvavgr_hu, gvec_vvv, 32, MO_16, do_vavgr_u)
TRANS(xvavgr_wu, gvec_vvv, 32, MO_32, do_vavgr_u)
TRANS(xvavgr_du, gvec_vvv, 32, MO_64, do_vavgr_u)
+TRANS(xvabsd_b, gvec_vvv, 32, MO_8, do_vabsd_s)
+TRANS(xvabsd_h, gvec_vvv, 32, MO_16, do_vabsd_s)
+TRANS(xvabsd_w, gvec_vvv, 32, MO_32, do_vabsd_s)
+TRANS(xvabsd_d, gvec_vvv, 32, MO_64, do_vabsd_s)
+TRANS(xvabsd_bu, gvec_vvv, 32, MO_8, do_vabsd_u)
+TRANS(xvabsd_hu, gvec_vvv, 32, MO_16, do_vabsd_u)
+TRANS(xvabsd_wu, gvec_vvv, 32, MO_32, do_vabsd_u)
+TRANS(xvabsd_du, gvec_vvv, 32, MO_64, do_vabsd_u)
+
TRANS(xvreplgr2vr_b, gvec_dup, 32, MO_8)
TRANS(xvreplgr2vr_h, gvec_dup, 32, MO_16)
TRANS(xvreplgr2vr_w, gvec_dup, 32, MO_32)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index a2cb39750d..c086ee9b22 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1423,6 +1423,15 @@ xvavgr_hu 0111 01000110 10101 ..... ..... .....
@vvv
xvavgr_wu 0111 01000110 10110 ..... ..... ..... @vvv
xvavgr_du 0111 01000110 10111 ..... ..... ..... @vvv
+xvabsd_b 0111 01000110 00000 ..... ..... ..... @vvv
+xvabsd_h 0111 01000110 00001 ..... ..... ..... @vvv
+xvabsd_w 0111 01000110 00010 ..... ..... ..... @vvv
+xvabsd_d 0111 01000110 00011 ..... ..... ..... @vvv
+xvabsd_bu 0111 01000110 00100 ..... ..... ..... @vvv
+xvabsd_hu 0111 01000110 00101 ..... ..... ..... @vvv
+xvabsd_wu 0111 01000110 00110 ..... ..... ..... @vvv
+xvabsd_du 0111 01000110 00111 ..... ..... ..... @vvv
+
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
diff --git a/target/loongarch/vec.h b/target/loongarch/vec.h
index 361bf87896..ef2897fc10 100644
--- a/target/loongarch/vec.h
+++ b/target/loongarch/vec.h
@@ -53,4 +53,6 @@
#define DO_VAVG(a, b) ((a >> 1) + (b >> 1) + (a & b & 1))
#define DO_VAVGR(a, b) ((a >> 1) + (b >> 1) + ((a | b) & 1))
+#define DO_VABSD(a, b) ((a > b) ? (a - b) : (b - a))
+
#endif /* LOONGARCH_VEC_H */
diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c
index 56997455de..99a1601d4e 100644
--- a/target/loongarch/vec_helper.c
+++ b/target/loongarch/vec_helper.c
@@ -372,8 +372,6 @@ DO_3OP(vavgr_hu, 16, UH, DO_VAVGR)
DO_3OP(vavgr_wu, 32, UW, DO_VAVGR)
DO_3OP(vavgr_du, 64, UD, DO_VAVGR)
-#define DO_VABSD(a, b) ((a > b) ? (a -b) : (b-a))
-
DO_3OP(vabsd_b, 8, B, DO_VABSD)
DO_3OP(vabsd_h, 16, H, DO_VABSD)
DO_3OP(vabsd_w, 32, W, DO_VABSD)
--
2.39.1
- [PATCH v2 29/46] target/loongarch: Implement xvsrlrn xvsrarn, (continued)
- [PATCH v2 29/46] target/loongarch: Implement xvsrlrn xvsrarn, Song Gao, 2023/06/30
- [PATCH v2 38/46] target/loongarch: Implement xvseq xvsle xvslt, Song Gao, 2023/06/30
- [PATCH v2 37/46] target/loongarch: Implement LASX fpu fcvt instructions, Song Gao, 2023/06/30
- [PATCH v2 44/46] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i xvextrins, Song Gao, 2023/06/30
- [PATCH v2 46/46] target/loongarch: CPUCFG support LASX, Song Gao, 2023/06/30
- [PATCH v2 39/46] target/loongarch: Implement xvfcmp, Song Gao, 2023/06/30
- [PATCH v2 41/46] target/loongarch: Implement xvinsgr2vr xvpickve2gr, Song Gao, 2023/06/30
- [PATCH v2 45/46] target/loongarch: Implement xvld xvst, Song Gao, 2023/06/30
- [PATCH v2 43/46] target/loongarch: Implement xvpack xvpick xvilv{l/h}, Song Gao, 2023/06/30
- [PATCH v2 40/46] target/loongarch: Implement xvbitsel xvset, Song Gao, 2023/06/30
- [PATCH v2 12/46] target/loongarch: Implement xvabsd,
Song Gao <=
- [PATCH v2 36/46] target/loongarch: Implement LASX fpu arith instructions, Song Gao, 2023/06/30
- [PATCH v2 35/46] target/loongarch: Implement xvfrstp, Song Gao, 2023/06/30
- [PATCH v2 24/46] target/loongarch: Implement LASX logic instructions, Song Gao, 2023/06/30
- [PATCH v2 42/46] target/loongarch: Implement xvreplve xvinsve0 xvpickve xvb{sll/srl}v, Song Gao, 2023/06/30
- [PATCH v2 32/46] target/loongarch: Implement xvclo xvclz, Song Gao, 2023/06/30
- [PATCH v2 11/46] target/loongarch: Implement xavg/xvagr, Song Gao, 2023/06/30
- [PATCH v2 31/46] target/loongarch: Implement xvssrlrn xvssrarn, Song Gao, 2023/06/30
- [PATCH v2 30/46] target/loongarch: Implement xvssrln xvssran, Song Gao, 2023/06/30
- [PATCH v2 27/46] target/loongarch: Implement xvsrlr xvsrar, Song Gao, 2023/06/30