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[PATCH v2 29/46] target/loongarch: Implement xvsrlrn xvsrarn
|
From: |
Song Gao |
|
Subject: |
[PATCH v2 29/46] target/loongarch: Implement xvsrlrn xvsrarn |
|
Date: |
Fri, 30 Jun 2023 15:58:47 +0800 |
This patch includes:
- XVSRLRN.{B.H/H.W/W.D};
- XVSRARN.{B.H/H.W/W.D};
- XVSRLRNI.{B.H/H.W/W.D/D.Q};
- XVSRARNI.{B.H/H.W/W.D/D.Q}.
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/disas.c | 16 ++
target/loongarch/helper.h | 30 +--
target/loongarch/insn_trans/trans_lasx.c.inc | 16 ++
target/loongarch/insns.decode | 16 ++
target/loongarch/vec_helper.c | 206 ++++++++++++-------
5 files changed, 189 insertions(+), 95 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 14b526abd6..04b6ea713d 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -2120,6 +2120,22 @@ INSN_LASX(xvsrani_h_w, vv_i)
INSN_LASX(xvsrani_w_d, vv_i)
INSN_LASX(xvsrani_d_q, vv_i)
+INSN_LASX(xvsrlrn_b_h, vvv)
+INSN_LASX(xvsrlrn_h_w, vvv)
+INSN_LASX(xvsrlrn_w_d, vvv)
+INSN_LASX(xvsrarn_b_h, vvv)
+INSN_LASX(xvsrarn_h_w, vvv)
+INSN_LASX(xvsrarn_w_d, vvv)
+
+INSN_LASX(xvsrlrni_b_h, vv_i)
+INSN_LASX(xvsrlrni_h_w, vv_i)
+INSN_LASX(xvsrlrni_w_d, vv_i)
+INSN_LASX(xvsrlrni_d_q, vv_i)
+INSN_LASX(xvsrarni_b_h, vv_i)
+INSN_LASX(xvsrarni_h_w, vv_i)
+INSN_LASX(xvsrarni_w_d, vv_i)
+INSN_LASX(xvsrarni_d_q, vv_i)
+
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index edef8c2135..a708b4321f 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -409,21 +409,21 @@ DEF_HELPER_5(vsrani_h_w, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vsrani_w_d, void, env, i32, i32, i32, i32)
DEF_HELPER_5(vsrani_d_q, void, env, i32, i32, i32, i32)
-DEF_HELPER_4(vsrlrn_b_h, void, env, i32, i32, i32)
-DEF_HELPER_4(vsrlrn_h_w, void, env, i32, i32, i32)
-DEF_HELPER_4(vsrlrn_w_d, void, env, i32, i32, i32)
-DEF_HELPER_4(vsrarn_b_h, void, env, i32, i32, i32)
-DEF_HELPER_4(vsrarn_h_w, void, env, i32, i32, i32)
-DEF_HELPER_4(vsrarn_w_d, void, env, i32, i32, i32)
-
-DEF_HELPER_4(vsrlrni_b_h, void, env, i32, i32, i32)
-DEF_HELPER_4(vsrlrni_h_w, void, env, i32, i32, i32)
-DEF_HELPER_4(vsrlrni_w_d, void, env, i32, i32, i32)
-DEF_HELPER_4(vsrlrni_d_q, void, env, i32, i32, i32)
-DEF_HELPER_4(vsrarni_b_h, void, env, i32, i32, i32)
-DEF_HELPER_4(vsrarni_h_w, void, env, i32, i32, i32)
-DEF_HELPER_4(vsrarni_w_d, void, env, i32, i32, i32)
-DEF_HELPER_4(vsrarni_d_q, void, env, i32, i32, i32)
+DEF_HELPER_5(vsrlrn_b_h, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vsrlrn_h_w, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vsrlrn_w_d, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vsrarn_b_h, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vsrarn_h_w, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vsrarn_w_d, void, env, i32, i32, i32, i32)
+
+DEF_HELPER_5(vsrlrni_b_h, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vsrlrni_h_w, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vsrlrni_w_d, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vsrlrni_d_q, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vsrarni_b_h, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vsrarni_h_w, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vsrarni_w_d, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vsrarni_d_q, void, env, i32, i32, i32, i32)
DEF_HELPER_4(vssrln_b_h, void, env, i32, i32, i32)
DEF_HELPER_4(vssrln_h_w, void, env, i32, i32, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index a1c3432eec..58f7c3bbc0 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -496,6 +496,22 @@ TRANS(xvsrani_h_w, gen_vv_i, 32, gen_helper_vsrani_h_w)
TRANS(xvsrani_w_d, gen_vv_i, 32, gen_helper_vsrani_w_d)
TRANS(xvsrani_d_q, gen_vv_i, 32, gen_helper_vsrani_d_q)
+TRANS(xvsrlrn_b_h, gen_vvv, 32, gen_helper_vsrlrn_b_h)
+TRANS(xvsrlrn_h_w, gen_vvv, 32, gen_helper_vsrlrn_h_w)
+TRANS(xvsrlrn_w_d, gen_vvv, 32, gen_helper_vsrlrn_w_d)
+TRANS(xvsrarn_b_h, gen_vvv, 32, gen_helper_vsrarn_b_h)
+TRANS(xvsrarn_h_w, gen_vvv, 32, gen_helper_vsrarn_h_w)
+TRANS(xvsrarn_w_d, gen_vvv, 32, gen_helper_vsrarn_w_d)
+
+TRANS(xvsrlrni_b_h, gen_vv_i, 32, gen_helper_vsrlrni_b_h)
+TRANS(xvsrlrni_h_w, gen_vv_i, 32, gen_helper_vsrlrni_h_w)
+TRANS(xvsrlrni_w_d, gen_vv_i, 32, gen_helper_vsrlrni_w_d)
+TRANS(xvsrlrni_d_q, gen_vv_i, 32, gen_helper_vsrlrni_d_q)
+TRANS(xvsrarni_b_h, gen_vv_i, 32, gen_helper_vsrarni_b_h)
+TRANS(xvsrarni_h_w, gen_vv_i, 32, gen_helper_vsrarni_h_w)
+TRANS(xvsrarni_w_d, gen_vv_i, 32, gen_helper_vsrarni_w_d)
+TRANS(xvsrarni_d_q, gen_vv_i, 32, gen_helper_vsrarni_d_q)
+
TRANS(xvreplgr2vr_b, gvec_dup, 32, MO_8)
TRANS(xvreplgr2vr_h, gvec_dup, 32, MO_16)
TRANS(xvreplgr2vr_w, gvec_dup, 32, MO_32)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 204dcfa075..d7c50b14ca 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1694,6 +1694,22 @@ xvsrani_h_w 0111 01110101 10001 ..... ..... .....
@vv_ui5
xvsrani_w_d 0111 01110101 1001 ...... ..... ..... @vv_ui6
xvsrani_d_q 0111 01110101 101 ....... ..... ..... @vv_ui7
+xvsrlrn_b_h 0111 01001111 10001 ..... ..... ..... @vvv
+xvsrlrn_h_w 0111 01001111 10010 ..... ..... ..... @vvv
+xvsrlrn_w_d 0111 01001111 10011 ..... ..... ..... @vvv
+xvsrarn_b_h 0111 01001111 10101 ..... ..... ..... @vvv
+xvsrarn_h_w 0111 01001111 10110 ..... ..... ..... @vvv
+xvsrarn_w_d 0111 01001111 10111 ..... ..... ..... @vvv
+
+xvsrlrni_b_h 0111 01110100 01000 1 .... ..... ..... @vv_ui4
+xvsrlrni_h_w 0111 01110100 01001 ..... ..... ..... @vv_ui5
+xvsrlrni_w_d 0111 01110100 0101 ...... ..... ..... @vv_ui6
+xvsrlrni_d_q 0111 01110100 011 ....... ..... ..... @vv_ui7
+xvsrarni_b_h 0111 01110101 11000 1 .... ..... ..... @vv_ui4
+xvsrarni_h_w 0111 01110101 11001 ..... ..... ..... @vv_ui5
+xvsrarni_w_d 0111 01110101 1101 ...... ..... ..... @vv_ui6
+xvsrarni_d_q 0111 01110101 111 ....... ..... ..... @vv_ui7
+
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c
index 8083c24ea7..bad3fe2952 100644
--- a/target/loongarch/vec_helper.c
+++ b/target/loongarch/vec_helper.c
@@ -1256,80 +1256,111 @@ VSRANI(vsrani_b_h, 16, B, H)
VSRANI(vsrani_h_w, 32, H, W)
VSRANI(vsrani_w_d, 64, W, D)
-#define VSRLRN(NAME, BIT, T, E1, E2) \
-void HELPER(NAME)(CPULoongArchState *env, \
- uint32_t vd, uint32_t vj, uint32_t vk) \
-{ \
- int i; \
- VReg *Vd = &(env->fpr[vd].vreg); \
- VReg *Vj = &(env->fpr[vj].vreg); \
- VReg *Vk = &(env->fpr[vk].vreg); \
- \
- for (i = 0; i < LSX_LEN/BIT; i++) { \
- Vd->E1(i) = do_vsrlr_ ## E2(Vj->E2(i), ((T)Vk->E2(i))%BIT); \
- } \
- Vd->D(1) = 0; \
+#define VSRLRN(NAME, BIT, E1, E2, E3) \
+void HELPER(NAME)(CPULoongArchState *env, uint32_t oprsz, \
+ uint32_t vd, uint32_t vj, uint32_t vk) \
+{ \
+ int i, max; \
+ VReg *Vd = &(env->fpr[vd].vreg); \
+ VReg *Vj = &(env->fpr[vj].vreg); \
+ VReg *Vk = &(env->fpr[vk].vreg); \
+ \
+ max = LSX_LEN / BIT; \
+ for (i = 0; i < max; i++) { \
+ Vd->E1(i) = do_vsrlr_ ## E2(Vj->E2(i), Vk->E3(i) % BIT); \
+ if (oprsz == 32) { \
+ Vd->E1(i + max * 2 ) = do_vsrlr_ ##E2(Vj->E2(i + max), \
+ Vk->E3(i + max) % BIT); \
+ } \
+ } \
+ Vd->D(1) = 0; \
+ if (oprsz == 32) { \
+ Vd->D(3) = 0; \
+ } \
}
-VSRLRN(vsrlrn_b_h, 16, uint16_t, B, H)
-VSRLRN(vsrlrn_h_w, 32, uint32_t, H, W)
-VSRLRN(vsrlrn_w_d, 64, uint64_t, W, D)
+VSRLRN(vsrlrn_b_h, 16, B, H, UH)
+VSRLRN(vsrlrn_h_w, 32, H, W, UW)
+VSRLRN(vsrlrn_w_d, 64, W, D, UD)
-#define VSRARN(NAME, BIT, T, E1, E2) \
-void HELPER(NAME)(CPULoongArchState *env, \
- uint32_t vd, uint32_t vj, uint32_t vk) \
-{ \
- int i; \
- VReg *Vd = &(env->fpr[vd].vreg); \
- VReg *Vj = &(env->fpr[vj].vreg); \
- VReg *Vk = &(env->fpr[vk].vreg); \
- \
- for (i = 0; i < LSX_LEN/BIT; i++) { \
- Vd->E1(i) = do_vsrar_ ## E2(Vj->E2(i), ((T)Vk->E2(i))%BIT); \
- } \
- Vd->D(1) = 0; \
+#define VSRARN(NAME, BIT, E1, E2, E3) \
+void HELPER(NAME)(CPULoongArchState *env, uint32_t oprsz, \
+ uint32_t vd, uint32_t vj, uint32_t vk) \
+{ \
+ int i, max; \
+ VReg *Vd = &(env->fpr[vd].vreg); \
+ VReg *Vj = &(env->fpr[vj].vreg); \
+ VReg *Vk = &(env->fpr[vk].vreg); \
+ \
+ max = LSX_LEN / BIT; \
+ for (i = 0; i < max; i++) { \
+ Vd->E1(i) = do_vsrar_ ## E2(Vj->E2(i), Vk->E3(i) % BIT); \
+ if (oprsz == 32) { \
+ Vd->E1(i + max * 2) = do_vsrar_ ## E2(Vj->E2(i + max), \
+ Vk->E3(i + max) % BIT); \
+ } \
+ } \
+ Vd->D(1) = 0; \
+ if (oprsz == 32) { \
+ Vd->D(3) = 0; \
+ } \
}
-VSRARN(vsrarn_b_h, 16, uint8_t, B, H)
-VSRARN(vsrarn_h_w, 32, uint16_t, H, W)
-VSRARN(vsrarn_w_d, 64, uint32_t, W, D)
+VSRARN(vsrarn_b_h, 16, B, H, UH)
+VSRARN(vsrarn_h_w, 32, H, W, UW)
+VSRARN(vsrarn_w_d, 64, W, D, UD)
-#define VSRLRNI(NAME, BIT, E1, E2) \
-void HELPER(NAME)(CPULoongArchState *env, \
- uint32_t vd, uint32_t vj, uint32_t imm) \
-{ \
- int i, max; \
- VReg temp; \
- VReg *Vd = &(env->fpr[vd].vreg); \
- VReg *Vj = &(env->fpr[vj].vreg); \
- \
- temp.D(0) = 0; \
- temp.D(1) = 0; \
- max = LSX_LEN/BIT; \
- for (i = 0; i < max; i++) { \
- temp.E1(i) = do_vsrlr_ ## E2(Vj->E2(i), imm); \
- temp.E1(i + max) = do_vsrlr_ ## E2(Vd->E2(i), imm); \
- } \
- *Vd = temp; \
+#define VSRLRNI(NAME, BIT, E1, E2) \
+void HELPER(NAME)(CPULoongArchState *env, uint32_t oprsz, \
+ uint32_t vd, uint32_t vj, uint32_t imm) \
+{ \
+ int i, max; \
+ VReg temp; \
+ VReg *Vd = &(env->fpr[vd].vreg); \
+ VReg *Vj = &(env->fpr[vj].vreg); \
+ \
+ temp.Q(0) = int128_zero(); \
+ if (oprsz == 32) { \
+ temp.Q(1) = int128_zero(); \
+ } \
+ max = LSX_LEN / BIT; \
+ for (i = 0; i < max; i++) { \
+ temp.E1(i) = do_vsrlr_ ## E2(Vj->E2(i), imm); \
+ temp.E1(i + max) = do_vsrlr_ ## E2(Vd->E2(i), imm); \
+ if (oprsz == 32) { \
+ temp.E1(i + max * 2) = do_vsrlr_ ## E2(Vj->E2(i + max), imm); \
+ temp.E1(i + max * 3) = do_vsrlr_ ## E2(Vd->E2(i + max), imm); \
+ } \
+ } \
+ *Vd = temp; \
}
-void HELPER(vsrlrni_d_q)(CPULoongArchState *env,
+void HELPER(vsrlrni_d_q)(CPULoongArchState *env, uint32_t oprsz,
uint32_t vd, uint32_t vj, uint32_t imm)
{
VReg temp;
VReg *Vd = &(env->fpr[vd].vreg);
VReg *Vj = &(env->fpr[vj].vreg);
- Int128 r1, r2;
+ Int128 r1, r2, r3, r4;
if (imm == 0) {
temp.D(0) = int128_getlo(Vj->Q(0));
temp.D(1) = int128_getlo(Vd->Q(0));
+ if (oprsz == 32) {
+ temp.D(2) = int128_getlo(Vj->Q(1));
+ temp.D(3) = int128_getlo(Vd->Q(1));
+ }
} else {
- r1 = int128_and(int128_urshift(Vj->Q(0), (imm -1)), int128_one());
- r2 = int128_and(int128_urshift(Vd->Q(0), (imm -1)), int128_one());
-
- temp.D(0) = int128_getlo(int128_add(int128_urshift(Vj->Q(0), imm), r1));
- temp.D(1) = int128_getlo(int128_add(int128_urshift(Vd->Q(0), imm), r2));
+ r1 = int128_and(int128_urshift(Vj->Q(0), (imm - 1)), int128_one());
+ r2 = int128_and(int128_urshift(Vd->Q(0), (imm - 1)), int128_one());
+ temp.D(0) = int128_getlo(int128_add(int128_urshift(Vj->Q(0), imm),
r1));
+ temp.D(1) = int128_getlo(int128_add(int128_urshift(Vd->Q(0), imm),
r2));
+ if (oprsz == 32) {
+ r3 = int128_and(int128_urshift(Vj->Q(1), (imm - 1)), int128_one());
+ r4 = int128_and(int128_urshift(Vd->Q(1), (imm - 1)), int128_one());
+ temp.D(2) = int128_getlo(int128_add(int128_urshift(Vj->Q(1), imm),
r3));
+ temp.D(3) = int128_getlo(int128_add(int128_urshift(Vd->Q(1), imm),
r4));
+ }
}
*Vd = temp;
}
@@ -1338,42 +1369,57 @@ VSRLRNI(vsrlrni_b_h, 16, B, H)
VSRLRNI(vsrlrni_h_w, 32, H, W)
VSRLRNI(vsrlrni_w_d, 64, W, D)
-#define VSRARNI(NAME, BIT, E1, E2) \
-void HELPER(NAME)(CPULoongArchState *env, \
- uint32_t vd, uint32_t vj, uint32_t imm) \
-{ \
- int i, max; \
- VReg temp; \
- VReg *Vd = &(env->fpr[vd].vreg); \
- VReg *Vj = &(env->fpr[vj].vreg); \
- \
- temp.D(0) = 0; \
- temp.D(1) = 0; \
- max = LSX_LEN/BIT; \
- for (i = 0; i < max; i++) { \
- temp.E1(i) = do_vsrar_ ## E2(Vj->E2(i), imm); \
- temp.E1(i + max) = do_vsrar_ ## E2(Vd->E2(i), imm); \
- } \
- *Vd = temp; \
+#define VSRARNI(NAME, BIT, E1, E2) \
+void HELPER(NAME)(CPULoongArchState *env, uint32_t oprsz, \
+ uint32_t vd, uint32_t vj, uint32_t imm) \
+{ \
+ int i, max; \
+ VReg temp; \
+ VReg *Vd = &(env->fpr[vd].vreg); \
+ VReg *Vj = &(env->fpr[vj].vreg); \
+ \
+ temp.Q(0) = int128_zero(); \
+ if (oprsz == 32) { \
+ temp.Q(1) = int128_zero(); \
+ } \
+ max = LSX_LEN / BIT; \
+ for (i = 0; i < max; i++) { \
+ temp.E1(i) = do_vsrar_ ## E2(Vj->E2(i), imm); \
+ temp.E1(i + max) = do_vsrar_ ## E2(Vd->E2(i), imm); \
+ if (oprsz == 32) { \
+ temp.E1(i + max * 2) = do_vsrar_ ## E2(Vj->E2(i + max), imm); \
+ temp.E1(i + max * 3) = do_vsrar_ ## E2(Vd->E2(i + max), imm); \
+ } \
+ } \
+ *Vd = temp; \
}
-void HELPER(vsrarni_d_q)(CPULoongArchState *env,
+void HELPER(vsrarni_d_q)(CPULoongArchState *env, uint32_t oprsz,
uint32_t vd, uint32_t vj, uint32_t imm)
{
VReg temp;
VReg *Vd = &(env->fpr[vd].vreg);
VReg *Vj = &(env->fpr[vj].vreg);
- Int128 r1, r2;
+ Int128 r1, r2, r3, r4;
if (imm == 0) {
temp.D(0) = int128_getlo(Vj->Q(0));
temp.D(1) = int128_getlo(Vd->Q(0));
+ if (oprsz == 32) {
+ temp.D(2) = int128_getlo(Vj->Q(1));
+ temp.D(3) = int128_getlo(Vd->Q(1));
+ }
} else {
- r1 = int128_and(int128_rshift(Vj->Q(0), (imm -1)), int128_one());
- r2 = int128_and(int128_rshift(Vd->Q(0), (imm -1)), int128_one());
-
- temp.D(0) = int128_getlo(int128_add(int128_rshift(Vj->Q(0), imm), r1));
- temp.D(1) = int128_getlo(int128_add(int128_rshift(Vd->Q(0), imm), r2));
+ r1 = int128_and(int128_rshift(Vj->Q(0), (imm - 1)), int128_one());
+ r2 = int128_and(int128_rshift(Vd->Q(0), (imm - 1)), int128_one());
+ temp.D(0) = int128_getlo(int128_add(int128_rshift(Vj->Q(0), imm), r1));
+ temp.D(1) = int128_getlo(int128_add(int128_rshift(Vd->Q(0), imm), r2));
+ if (oprsz == 32) {
+ r3 = int128_and(int128_rshift(Vj->Q(1), (imm - 1)), int128_one());
+ r4 = int128_and(int128_rshift(Vd->Q(1), (imm - 1)), int128_one());
+ temp.D(2) = int128_getlo(int128_add(int128_rshift(Vj->Q(1), imm),
r3));
+ temp.D(3) = int128_getlo(int128_add(int128_rshift(Vd->Q(1), imm),
r4));
+ }
}
*Vd = temp;
}
--
2.39.1
- [PATCH v2 28/46] target/loongarch: Implement xvsrln xvsran, (continued)
- [PATCH v2 28/46] target/loongarch: Implement xvsrln xvsran, Song Gao, 2023/06/30
- [PATCH v2 23/46] target/loognarch: Implement xvldi, Song Gao, 2023/06/30
- [PATCH v2 26/46] target/loongarch: Implement xvsllwil xvextl, Song Gao, 2023/06/30
- [PATCH v2 34/46] target/loongarch: Implement xvbitclr xvbitset xvbitrev, Song Gao, 2023/06/30
- [PATCH v2 17/46] target/loongarch; Implement xvdiv/xvmod, Song Gao, 2023/06/30
- [PATCH v2 13/46] target/loongarch: Implement xvadda, Song Gao, 2023/06/30
- [PATCH v2 18/46] target/loongarch: Implement xvsat, Song Gao, 2023/06/30
- [PATCH v2 21/46] target/loongarch: Implement xvsigncov, Song Gao, 2023/06/30
- [PATCH v2 25/46] target/loongarch: Implement xvsll xvsrl xvsra xvrotr, Song Gao, 2023/06/30
- [PATCH v2 33/46] target/loongarch: Implement xvpcnt, Song Gao, 2023/06/30
- [PATCH v2 29/46] target/loongarch: Implement xvsrlrn xvsrarn,
Song Gao <=
- [PATCH v2 38/46] target/loongarch: Implement xvseq xvsle xvslt, Song Gao, 2023/06/30
- [PATCH v2 37/46] target/loongarch: Implement LASX fpu fcvt instructions, Song Gao, 2023/06/30
- [PATCH v2 44/46] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i xvextrins, Song Gao, 2023/06/30
- [PATCH v2 46/46] target/loongarch: CPUCFG support LASX, Song Gao, 2023/06/30
- [PATCH v2 39/46] target/loongarch: Implement xvfcmp, Song Gao, 2023/06/30
- [PATCH v2 41/46] target/loongarch: Implement xvinsgr2vr xvpickve2gr, Song Gao, 2023/06/30
- [PATCH v2 45/46] target/loongarch: Implement xvld xvst, Song Gao, 2023/06/30
- [PATCH v2 43/46] target/loongarch: Implement xvpack xvpick xvilv{l/h}, Song Gao, 2023/06/30
- [PATCH v2 40/46] target/loongarch: Implement xvbitsel xvset, Song Gao, 2023/06/30
- [PATCH v2 12/46] target/loongarch: Implement xvabsd, Song Gao, 2023/06/30