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[PATCH v2 17/46] target/loongarch; Implement xvdiv/xvmod
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From: |
Song Gao |
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Subject: |
[PATCH v2 17/46] target/loongarch; Implement xvdiv/xvmod |
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Date: |
Fri, 30 Jun 2023 15:58:35 +0800 |
This patch includes:
- XVDIV.{B/H/W/D}[U];
- XVMOD.{B/H/W/D}[U].
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
target/loongarch/disas.c | 17 +++++++++++
target/loongarch/helper.h | 32 ++++++++++----------
target/loongarch/insn_trans/trans_lasx.c.inc | 17 +++++++++++
target/loongarch/insns.decode | 17 +++++++++++
target/loongarch/vec.h | 7 +++++
target/loongarch/vec_helper.c | 15 +++------
6 files changed, 79 insertions(+), 26 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index b115fe8315..72df9f0b08 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -1962,6 +1962,23 @@ INSN_LASX(xvmaddwod_w_hu_h, vvv)
INSN_LASX(xvmaddwod_d_wu_w, vvv)
INSN_LASX(xvmaddwod_q_du_d, vvv)
+INSN_LASX(xvdiv_b, vvv)
+INSN_LASX(xvdiv_h, vvv)
+INSN_LASX(xvdiv_w, vvv)
+INSN_LASX(xvdiv_d, vvv)
+INSN_LASX(xvdiv_bu, vvv)
+INSN_LASX(xvdiv_hu, vvv)
+INSN_LASX(xvdiv_wu, vvv)
+INSN_LASX(xvdiv_du, vvv)
+INSN_LASX(xvmod_b, vvv)
+INSN_LASX(xvmod_h, vvv)
+INSN_LASX(xvmod_w, vvv)
+INSN_LASX(xvmod_d, vvv)
+INSN_LASX(xvmod_bu, vvv)
+INSN_LASX(xvmod_hu, vvv)
+INSN_LASX(xvmod_wu, vvv)
+INSN_LASX(xvmod_du, vvv)
+
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index b0dd098e26..f018d6c754 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -304,22 +304,22 @@ DEF_HELPER_FLAGS_4(vmaddwod_h_bu_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmaddwod_w_hu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vmaddwod_d_wu_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
-DEF_HELPER_4(vdiv_b, void, env, i32, i32, i32)
-DEF_HELPER_4(vdiv_h, void, env, i32, i32, i32)
-DEF_HELPER_4(vdiv_w, void, env, i32, i32, i32)
-DEF_HELPER_4(vdiv_d, void, env, i32, i32, i32)
-DEF_HELPER_4(vdiv_bu, void, env, i32, i32, i32)
-DEF_HELPER_4(vdiv_hu, void, env, i32, i32, i32)
-DEF_HELPER_4(vdiv_wu, void, env, i32, i32, i32)
-DEF_HELPER_4(vdiv_du, void, env, i32, i32, i32)
-DEF_HELPER_4(vmod_b, void, env, i32, i32, i32)
-DEF_HELPER_4(vmod_h, void, env, i32, i32, i32)
-DEF_HELPER_4(vmod_w, void, env, i32, i32, i32)
-DEF_HELPER_4(vmod_d, void, env, i32, i32, i32)
-DEF_HELPER_4(vmod_bu, void, env, i32, i32, i32)
-DEF_HELPER_4(vmod_hu, void, env, i32, i32, i32)
-DEF_HELPER_4(vmod_wu, void, env, i32, i32, i32)
-DEF_HELPER_4(vmod_du, void, env, i32, i32, i32)
+DEF_HELPER_5(vdiv_b, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vdiv_h, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vdiv_w, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vdiv_d, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vdiv_bu, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vdiv_hu, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vdiv_wu, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vdiv_du, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vmod_b, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vmod_h, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vmod_w, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vmod_d, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vmod_bu, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vmod_hu, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vmod_wu, void, env, i32, i32, i32, i32)
+DEF_HELPER_5(vmod_du, void, env, i32, i32, i32, i32)
DEF_HELPER_FLAGS_4(vsat_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
DEF_HELPER_FLAGS_4(vsat_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
diff --git a/target/loongarch/insn_trans/trans_lasx.c.inc
b/target/loongarch/insn_trans/trans_lasx.c.inc
index 2c2fae91b9..0064ffa6cb 100644
--- a/target/loongarch/insn_trans/trans_lasx.c.inc
+++ b/target/loongarch/insn_trans/trans_lasx.c.inc
@@ -344,6 +344,23 @@ TRANS(xvmaddwod_h_bu_b, gvec_vvv, 32, MO_8,
do_vmaddwod_u_s)
TRANS(xvmaddwod_w_hu_h, gvec_vvv, 32, MO_16, do_vmaddwod_u_s)
TRANS(xvmaddwod_d_wu_w, gvec_vvv, 32, MO_32, do_vmaddwod_u_s)
+TRANS(xvdiv_b, gen_vvv, 32, gen_helper_vdiv_b)
+TRANS(xvdiv_h, gen_vvv, 32, gen_helper_vdiv_h)
+TRANS(xvdiv_w, gen_vvv, 32, gen_helper_vdiv_w)
+TRANS(xvdiv_d, gen_vvv, 32, gen_helper_vdiv_d)
+TRANS(xvdiv_bu, gen_vvv, 32, gen_helper_vdiv_bu)
+TRANS(xvdiv_hu, gen_vvv, 32, gen_helper_vdiv_hu)
+TRANS(xvdiv_wu, gen_vvv, 32, gen_helper_vdiv_wu)
+TRANS(xvdiv_du, gen_vvv, 32, gen_helper_vdiv_du)
+TRANS(xvmod_b, gen_vvv, 32, gen_helper_vmod_b)
+TRANS(xvmod_h, gen_vvv, 32, gen_helper_vmod_h)
+TRANS(xvmod_w, gen_vvv, 32, gen_helper_vmod_w)
+TRANS(xvmod_d, gen_vvv, 32, gen_helper_vmod_d)
+TRANS(xvmod_bu, gen_vvv, 32, gen_helper_vmod_bu)
+TRANS(xvmod_hu, gen_vvv, 32, gen_helper_vmod_hu)
+TRANS(xvmod_wu, gen_vvv, 32, gen_helper_vmod_wu)
+TRANS(xvmod_du, gen_vvv, 32, gen_helper_vmod_du)
+
TRANS(xvreplgr2vr_b, gvec_dup, 32, MO_8)
TRANS(xvreplgr2vr_h, gvec_dup, 32, MO_16)
TRANS(xvreplgr2vr_w, gvec_dup, 32, MO_32)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index d6fb51ae64..fa25c876b4 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -1545,6 +1545,23 @@ xvmaddwod_w_hu_h 0111 01001011 11101 ..... ..... .....
@vvv
xvmaddwod_d_wu_w 0111 01001011 11110 ..... ..... ..... @vvv
xvmaddwod_q_du_d 0111 01001011 11111 ..... ..... ..... @vvv
+xvdiv_b 0111 01001110 00000 ..... ..... ..... @vvv
+xvdiv_h 0111 01001110 00001 ..... ..... ..... @vvv
+xvdiv_w 0111 01001110 00010 ..... ..... ..... @vvv
+xvdiv_d 0111 01001110 00011 ..... ..... ..... @vvv
+xvmod_b 0111 01001110 00100 ..... ..... ..... @vvv
+xvmod_h 0111 01001110 00101 ..... ..... ..... @vvv
+xvmod_w 0111 01001110 00110 ..... ..... ..... @vvv
+xvmod_d 0111 01001110 00111 ..... ..... ..... @vvv
+xvdiv_bu 0111 01001110 01000 ..... ..... ..... @vvv
+xvdiv_hu 0111 01001110 01001 ..... ..... ..... @vvv
+xvdiv_wu 0111 01001110 01010 ..... ..... ..... @vvv
+xvdiv_du 0111 01001110 01011 ..... ..... ..... @vvv
+xvmod_bu 0111 01001110 01100 ..... ..... ..... @vvv
+xvmod_hu 0111 01001110 01101 ..... ..... ..... @vvv
+xvmod_wu 0111 01001110 01110 ..... ..... ..... @vvv
+xvmod_du 0111 01001110 01111 ..... ..... ..... @vvv
+
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr
diff --git a/target/loongarch/vec.h b/target/loongarch/vec.h
index 1abc6a3da0..c2d08a8e87 100644
--- a/target/loongarch/vec.h
+++ b/target/loongarch/vec.h
@@ -65,4 +65,11 @@
#define DO_MADD(a, b, c) (a + b * c)
#define DO_MSUB(a, b, c) (a - b * c)
+#define DO_DIVU(N, M) (unlikely(M == 0) ? 0 : N / M)
+#define DO_REMU(N, M) (unlikely(M == 0) ? 0 : N % M)
+#define DO_DIV(N, M) (unlikely(M == 0) ? 0 :\
+ unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
+#define DO_REM(N, M) (unlikely(M == 0) ? 0 :\
+ unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
+
#endif /* LOONGARCH_VEC_H */
diff --git a/target/loongarch/vec_helper.c b/target/loongarch/vec_helper.c
index 367b794853..7b2433c962 100644
--- a/target/loongarch/vec_helper.c
+++ b/target/loongarch/vec_helper.c
@@ -618,22 +618,17 @@ VMADDWOD_U_S(vmaddwod_h_bu_b, 16, H, UH, B, UB, DO_MUL)
VMADDWOD_U_S(vmaddwod_w_hu_h, 32, W, UW, H, UH, DO_MUL)
VMADDWOD_U_S(vmaddwod_d_wu_w, 64, D, UD, W, UW, DO_MUL)
-#define DO_DIVU(N, M) (unlikely(M == 0) ? 0 : N / M)
-#define DO_REMU(N, M) (unlikely(M == 0) ? 0 : N % M)
-#define DO_DIV(N, M) (unlikely(M == 0) ? 0 :\
- unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
-#define DO_REM(N, M) (unlikely(M == 0) ? 0 :\
- unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
-
#define VDIV(NAME, BIT, E, DO_OP) \
-void HELPER(NAME)(CPULoongArchState *env, \
+void HELPER(NAME)(CPULoongArchState *env, uint32_t oprsz, \
uint32_t vd, uint32_t vj, uint32_t vk) \
{ \
- int i; \
+ int i, len; \
VReg *Vd = &(env->fpr[vd].vreg); \
VReg *Vj = &(env->fpr[vj].vreg); \
VReg *Vk = &(env->fpr[vk].vreg); \
- for (i = 0; i < LSX_LEN/BIT; i++) { \
+ \
+ len = (oprsz == 16) ? LSX_LEN : LASX_LEN; \
+ for (i = 0; i < len / BIT; i++) { \
Vd->E(i) = DO_OP(Vj->E(i), Vk->E(i)); \
} \
}
--
2.39.1
- [PATCH v2 15/46] target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}, (continued)
- [PATCH v2 15/46] target/loongarch: Implement xvmul/xvmuh/xvmulw{ev/od}, Song Gao, 2023/06/30
- [PATCH v2 16/46] target/loongarch: Implement xvmadd/xvmsub/xvmaddw{ev/od}, Song Gao, 2023/06/30
- [PATCH v2 14/46] target/loongarch: Implement xvmax/xvmin, Song Gao, 2023/06/30
- [PATCH v2 19/46] target/loongarch: Implement xvexth, Song Gao, 2023/06/30
- [PATCH v2 22/46] target/loongarch: Implement xvmskltz/xvmskgez/xvmsknz, Song Gao, 2023/06/30
- [PATCH v2 20/46] target/loongarch: Implement vext2xv, Song Gao, 2023/06/30
- [PATCH v2 28/46] target/loongarch: Implement xvsrln xvsran, Song Gao, 2023/06/30
- [PATCH v2 23/46] target/loognarch: Implement xvldi, Song Gao, 2023/06/30
- [PATCH v2 26/46] target/loongarch: Implement xvsllwil xvextl, Song Gao, 2023/06/30
- [PATCH v2 34/46] target/loongarch: Implement xvbitclr xvbitset xvbitrev, Song Gao, 2023/06/30
- [PATCH v2 17/46] target/loongarch; Implement xvdiv/xvmod,
Song Gao <=
- [PATCH v2 13/46] target/loongarch: Implement xvadda, Song Gao, 2023/06/30
- [PATCH v2 18/46] target/loongarch: Implement xvsat, Song Gao, 2023/06/30
- [PATCH v2 21/46] target/loongarch: Implement xvsigncov, Song Gao, 2023/06/30
- [PATCH v2 25/46] target/loongarch: Implement xvsll xvsrl xvsra xvrotr, Song Gao, 2023/06/30
- [PATCH v2 33/46] target/loongarch: Implement xvpcnt, Song Gao, 2023/06/30
- [PATCH v2 29/46] target/loongarch: Implement xvsrlrn xvsrarn, Song Gao, 2023/06/30
- [PATCH v2 38/46] target/loongarch: Implement xvseq xvsle xvslt, Song Gao, 2023/06/30
- [PATCH v2 37/46] target/loongarch: Implement LASX fpu fcvt instructions, Song Gao, 2023/06/30
- [PATCH v2 44/46] target/loongarch: Implement xvshuf xvperm{i} xvshuf4i xvextrins, Song Gao, 2023/06/30
- [PATCH v2 46/46] target/loongarch: CPUCFG support LASX, Song Gao, 2023/06/30