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[PATCH v4 05/21] i386/cpu: Fix i/d-cache topology to core level for Inte
From: |
Zhao Liu |
Subject: |
[PATCH v4 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU |
Date: |
Thu, 14 Sep 2023 15:21:43 +0800 |
From: Zhao Liu <zhao1.liu@intel.com>
For i-cache and d-cache, current QEMU hardcodes the maximum IDs for CPUs
sharing cache (CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits
25:14]) to 0, and this means i-cache and d-cache are shared in the SMT
level.
This is correct if there's single thread per core, but is wrong for the
hyper threading case (one core contains multiple threads) since the
i-cache and d-cache are shared in the core level other than SMT level.
For AMD CPU, commit 8f4202fb1080 ("i386: Populate AMD Processor Cache
Information for cpuid 0x8000001D") has already introduced i/d cache
topology as core level by default.
Therefore, in order to be compatible with both multi-threaded and
single-threaded situations, we should set i-cache and d-cache be shared
at the core level by default.
This fix changes the default i/d cache topology from per-thread to
per-core. Potentially, this change in L1 cache topology may affect the
performance of the VM if the user does not specifically specify the
topology or bind the vCPU. However, the way to achieve optimal
performance should be to create a reasonable topology and set the
appropriate vCPU affinity without relying on QEMU's default topology
structure.
Fixes: 7e3482f82480 ("i386: Helpers to encode cache information consistently")
Suggested-by: Robert Hoo <robert.hu@linux.intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
Changes since v3:
* Change the description of current i/d cache encoding status to avoid
misleading to "architectural rules". (Xiaoyao)
Changes since v1:
* Split this fix from the patch named "i386/cpu: Fix number of
addressable IDs in CPUID.04H".
* Add the explanation of the impact on performance. (Xiaoyao)
---
target/i386/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 709c055c8468..c5c2a045e032 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6108,12 +6108,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
switch (count) {
case 0: /* L1 dcache info */
encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
- 1, cs->nr_cores,
+ cs->nr_threads, cs->nr_cores,
eax, ebx, ecx, edx);
break;
case 1: /* L1 icache info */
encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
- 1, cs->nr_cores,
+ cs->nr_threads, cs->nr_cores,
eax, ebx, ecx, edx);
break;
case 2: /* L2 cache info */
--
2.34.1
- [PATCH v4 00/21] Support smp.clusters for x86 in QEMU, Zhao Liu, 2023/09/14
- [PATCH v4 03/21] softmmu: Fix CPUSTATE.nr_cores' calculation, Zhao Liu, 2023/09/14
- [PATCH v4 02/21] tests: Rename test-x86-cpuid.c to test-x86-topo.c, Zhao Liu, 2023/09/14
- [PATCH v4 01/21] i386: Fix comment style in topology.h, Zhao Liu, 2023/09/14
- [PATCH v4 04/21] hw/cpu: Update the comments of nr_cores and nr_dies, Zhao Liu, 2023/09/14
- [PATCH v4 05/21] i386/cpu: Fix i/d-cache topology to core level for Intel CPU,
Zhao Liu <=
- [PATCH v4 07/21] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid(), Zhao Liu, 2023/09/14
- [PATCH v4 08/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB], Zhao Liu, 2023/09/14
- [PATCH v4 06/21] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4], Zhao Liu, 2023/09/14
- [PATCH v4 10/21] i386: Introduce module-level cpu topology to CPUX86State, Zhao Liu, 2023/09/14
- [PATCH v4 11/21] i386: Support modules_per_die in X86CPUTopoInfo, Zhao Liu, 2023/09/14
- [PATCH v4 09/21] i386: Decouple CPUID[0x1F] subleaf with specific topology level, Zhao Liu, 2023/09/14
- [PATCH v4 12/21] i386: Expose module level in CPUID[0x1F], Zhao Liu, 2023/09/14
- [PATCH v4 13/21] i386: Support module_id in X86CPUTopoIDs, Zhao Liu, 2023/09/14