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Re: [PATCH v2 4/4] hw/cxl: Line length reductions
From: |
Jonathan Cameron |
Subject: |
Re: [PATCH v2 4/4] hw/cxl: Line length reductions |
Date: |
Tue, 19 Sep 2023 10:11:05 +0100 |
On Mon, 18 Sep 2023 16:48:45 +0000
Fan Ni <fan.ni@samsung.com> wrote:
> On Fri, Sep 15, 2023 at 06:04:18PM +0100, Jonathan Cameron wrote:
> > Michael Tsirkin observed that there were some unnecessarily
> > long lines in the CXL code in a recent review.
> > This patch is intended to rectify that where it does not
> > hurt readability.
> >
> > Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---
>
> One minor comment inline. Other than that, looks good to me.
> > diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
> > index c8d632d540..915c208209 100644
> > --- a/hw/cxl/cxl-component-utils.c
> > +++ b/hw/cxl/cxl-component-utils.c
> > @@ -240,7 +240,8 @@ static void hdm_init_common(uint32_t *reg_state,
> > uint32_t *write_msk,
> > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT,
> > 1);
> > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > INTERLEAVE_256B, 1);
> > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K,
> > 1);
> > - ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > POISON_ON_ERR_CAP, 0);
> > + ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> > + POISON_ON_ERR_CAP, 0);
> > ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_GLOBAL_CONTROL,
> > HDM_DECODER_ENABLE, 0);
> > write_msk[R_CXL_HDM_DECODER_GLOBAL_CONTROL] = 0x3;
> > @@ -263,13 +264,14 @@ static void hdm_init_common(uint32_t *reg_state,
> > uint32_t *write_msk,
> > }
> > }
> >
> > -void cxl_component_register_init_common(uint32_t *reg_state, uint32_t
> > *write_msk,
> > +void cxl_component_register_init_common(uint32_t *reg_state,
> > + uint32_t *write_msk,
> > enum reg_type type)
> > {
> > int caps = 0;
> >
> > /*
> > - * In CXL 2.0 the capabilities required for each CXL component are
> > such that,
> > + * In CXL2.0 the capabilities required for each CXL component are such
> > that,
>
> It seems we always leave a space between CXL and 2.0 in other
> places.
Indeed odd :) I'll put that space back in an rewrap that for v3.
Jonathan