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[PULL 11/17] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit f
From: |
Michael Tokarev |
Subject: |
[PULL 11/17] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS |
Date: |
Thu, 21 Sep 2023 11:35:00 +0300 |
From: Dave Jiang <dave.jiang@intel.com>
According to ACPI spec 6.5 5.2.28.4 System Locality Latency and Bandwidth
Information Structure, if the "Entry Base Unit" is 1024 for BW and the
matrix entry has the value of 100, the BW is 100 GB/s. So the
entry_base_unit should be changed from 1000 to 1024 given the comment notes
it's 16GB/s for .latency_bandwidth.
Fixes: 882877fc359d ("hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE")
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
---
hw/pci-bridge/cxl_upstream.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c
index 9159f48a8c..2b9cf0cc97 100644
--- a/hw/pci-bridge/cxl_upstream.c
+++ b/hw/pci-bridge/cxl_upstream.c
@@ -262,7 +262,7 @@ static int build_cdat_table(CDATSubHeader ***cdat_table,
void *priv)
.length = sslbis_size,
},
.data_type = HMATLB_DATA_TYPE_ACCESS_BANDWIDTH,
- .entry_base_unit = 1000,
+ .entry_base_unit = 1024,
},
};
--
2.39.2
- [PULL 01/17] ppc: spelling fixes, (continued)
- [PULL 01/17] ppc: spelling fixes, Michael Tokarev, 2023/09/21
- [PULL 06/17] hw/tpm: spelling fixes, Michael Tokarev, 2023/09/21
- [PULL 03/17] i386: spelling fixes, Michael Tokarev, 2023/09/21
- [PULL 02/17] bsd-user: spelling fixes, Michael Tokarev, 2023/09/21
- [PULL 05/17] hw/pci: spelling fixes, Michael Tokarev, 2023/09/21
- [PULL 09/17] hw/i386/pc: fix code comment on cumulative flash size, Michael Tokarev, 2023/09/21
- [PULL 10/17] hw/cxl: Fix CFMW config memory leak, Michael Tokarev, 2023/09/21
- [PULL 08/17] subprojects: Use the correct .git suffix in the repository URLs, Michael Tokarev, 2023/09/21
- [PULL 04/17] hw/net: spelling fixes, Michael Tokarev, 2023/09/21
- [PULL 07/17] hw/other: spelling fixes, Michael Tokarev, 2023/09/21
- [PULL 11/17] hw/pci-bridge/cxl_upstream: Fix bandwidth entry base unit for SSLBIS,
Michael Tokarev <=
- [PULL 12/17] hw/cxl/cxl_device: Replace magic number in CXLError definition, Michael Tokarev, 2023/09/21
- [PULL 14/17] hw/cxl: Fix out of bound array access, Michael Tokarev, 2023/09/21
- [PULL 13/17] docs/cxl: Change to lowercase as others, Michael Tokarev, 2023/09/21
- [PULL 15/17] hw/mem/cxl_type3: Add missing copyright and license notice, Michael Tokarev, 2023/09/21
- [PULL 16/17] docs/cxl: Cleanout some more aarch64 examples., Michael Tokarev, 2023/09/21
- [PULL 17/17] docs/devel/reset.rst: Correct function names, Michael Tokarev, 2023/09/21
- Re: [PULL 00/17] Trivial patches for 2023-09-21, Stefan Hajnoczi, 2023/09/21