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[PATCH 25/26] target/riscv: remove .instance_post_init
From: |
Paolo Bonzini |
Subject: |
[PATCH 25/26] target/riscv: remove .instance_post_init |
Date: |
Mon, 12 May 2025 11:52:25 +0200 |
Unlike other uses of .instance_post_init, accel_cpu_instance_init()
*registers* properties, and therefore must be run before
device_post_init() which sets them to their values from -global.
In order to move all registration of properties to .instance_init,
call accel_cpu_instance_init() at the end of riscv_cpu_init().
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/riscv/cpu.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f4d4abada75..2437d53d4bc 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1083,11 +1083,6 @@ static bool riscv_cpu_is_dynamic(Object *cpu_obj)
return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
}
-static void riscv_cpu_post_init(Object *obj)
-{
- accel_cpu_instance_init(CPU(obj));
-}
-
static void riscv_cpu_init(Object *obj)
{
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
@@ -1143,6 +1138,8 @@ static void riscv_cpu_init(Object *obj)
riscv_register_custom_csrs(cpu, mcc->def->custom_csrs);
}
#endif
+
+ accel_cpu_instance_init(CPU(obj));
}
typedef struct misa_ext_info {
@@ -2885,7 +2882,6 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.instance_size = sizeof(RISCVCPU),
.instance_align = __alignof(RISCVCPU),
.instance_init = riscv_cpu_init,
- .instance_post_init = riscv_cpu_post_init,
.abstract = true,
.class_size = sizeof(RISCVCPUClass),
.class_init = riscv_cpu_common_class_init,
--
2.49.0
- [PATCH 20/26] target/riscv: generalize custom CSR functionality, (continued)
- [PATCH 20/26] target/riscv: generalize custom CSR functionality, Paolo Bonzini, 2025/05/12
- [PATCH 19/26] target/riscv: th: make CSR insertion test a bit more intuitive, Paolo Bonzini, 2025/05/12
- [PATCH 17/26] target/riscv: convert ibex CPU models to RISCVCPUDef, Paolo Bonzini, 2025/05/12
- [PATCH 21/26] target/riscv: convert TT C906 to RISCVCPUDef, Paolo Bonzini, 2025/05/12
- [PATCH 22/26] target/riscv: convert TT Ascalon to RISCVCPUDef, Paolo Bonzini, 2025/05/12
- [PATCH 25/26] target/riscv: remove .instance_post_init,
Paolo Bonzini <=
- [PATCH 23/26] target/riscv: convert Ventana V1 to RISCVCPUDef, Paolo Bonzini, 2025/05/12
- [PATCH 26/26] qom: reverse order of instance_post_init calls, Paolo Bonzini, 2025/05/12
- [PATCH 24/26] target/riscv: convert Xiangshan Nanhu to RISCVCPUDef, Paolo Bonzini, 2025/05/12
- Re: [PATCH v5 00/26] target/riscv: SATP mode and CPU definition overhaul, Alistair Francis, 2025/05/15