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Re: [PATCH 25/26] target/riscv: remove .instance_post_init
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From: |
Paolo Bonzini |
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Subject: |
Re: [PATCH 25/26] target/riscv: remove .instance_post_init |
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Date: |
Mon, 12 May 2025 12:39:10 +0200 |
On Mon, May 12, 2025 at 12:35 PM Philippe Mathieu-Daudé
<philmd@linaro.org> wrote:
>
> Hi Paolo,
>
> On 12/5/25 11:52, Paolo Bonzini wrote:
> > Unlike other uses of .instance_post_init, accel_cpu_instance_init()
> > *registers* properties, and therefore must be run before
> > device_post_init() which sets them to their values from -global.
>
> Does x86_cpu_post_initfn() suffer from the same problem?
No, in fact this whole patch series is motivated by fixing a bug in
target/i386: target/i386 *wants* the order of instance_post_init to be
what patch 26 provides. This info was present in the postings up to
v3, see for example
https://patchew.org/QEMU/20250228102747.867770-1-pbonzini@redhat.com/.
Paolo
> > In order to move all registration of properties to .instance_init,
> > call accel_cpu_instance_init() at the end of riscv_cpu_init().
> >
> > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> > ---
> > target/riscv/cpu.c | 8 ++------
> > 1 file changed, 2 insertions(+), 6 deletions(-)
>
- [PATCH 19/26] target/riscv: th: make CSR insertion test a bit more intuitive, (continued)
- [PATCH 19/26] target/riscv: th: make CSR insertion test a bit more intuitive, Paolo Bonzini, 2025/05/12
- [PATCH 17/26] target/riscv: convert ibex CPU models to RISCVCPUDef, Paolo Bonzini, 2025/05/12
- [PATCH 21/26] target/riscv: convert TT C906 to RISCVCPUDef, Paolo Bonzini, 2025/05/12
- [PATCH 22/26] target/riscv: convert TT Ascalon to RISCVCPUDef, Paolo Bonzini, 2025/05/12
- [PATCH 25/26] target/riscv: remove .instance_post_init, Paolo Bonzini, 2025/05/12
- [PATCH 23/26] target/riscv: convert Ventana V1 to RISCVCPUDef, Paolo Bonzini, 2025/05/12
- [PATCH 26/26] qom: reverse order of instance_post_init calls, Paolo Bonzini, 2025/05/12
- [PATCH 24/26] target/riscv: convert Xiangshan Nanhu to RISCVCPUDef, Paolo Bonzini, 2025/05/12
- Re: [PATCH v5 00/26] target/riscv: SATP mode and CPU definition overhaul, Alistair Francis, 2025/05/15