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Re: [PATCH 19/50] pnv/xive2: VC_ENDC_WATCH_SPEC regs should read back WA
From: |
Caleb Schlossin |
Subject: |
Re: [PATCH 19/50] pnv/xive2: VC_ENDC_WATCH_SPEC regs should read back WATCH_FULL |
Date: |
Wed, 14 May 2025 09:37:04 -0500 |
User-agent: |
Mozilla Thunderbird |
Reviewed-by: Caleb Schlossin <calebs@linux.ibm.com>
On 5/11/25 10:10 PM, Nicholas Piggin wrote:
> Firmware expects to read back the WATCH_FULL bit from the VC_ENDC_WATCH_SPEC
> register, so don't clear it on read.
>
> Don't bother clearing the reads-as-zero CONFLICT bit because it's masked
> at write already.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> hw/intc/pnv_xive2.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
> index fcf5b2e75c..3c26cd6b77 100644
> --- a/hw/intc/pnv_xive2.c
> +++ b/hw/intc/pnv_xive2.c
> @@ -1329,7 +1329,6 @@ static uint64_t pnv_xive2_ic_vc_read(void *opaque,
> hwaddr offset,
> case VC_ENDC_WATCH2_SPEC:
> case VC_ENDC_WATCH3_SPEC:
> watch_engine = (offset - VC_ENDC_WATCH0_SPEC) >> 6;
> - xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT);
> pnv_xive2_endc_cache_watch_release(xive, watch_engine);
> val = xive->vc_regs[reg];
> break;
- Re: [PATCH 14/50] ppc/xive: Explicitly zero NSR after accepting, (continued)
- [PATCH 17/50] pnv/xive2: Support ESB Escalation, Nicholas Piggin, 2025/05/11
- [PATCH 15/50] ppc/xive: Move NSR decoding into helper functions, Nicholas Piggin, 2025/05/11
- [PATCH 19/50] pnv/xive2: VC_ENDC_WATCH_SPEC regs should read back WATCH_FULL, Nicholas Piggin, 2025/05/11
- [PATCH 20/50] pnv/xive2: Permit valid writes to VC/PC Flush Control registers, Nicholas Piggin, 2025/05/11
- [PATCH 16/50] ppc/xive: Fix pulling pool and phys contexts, Nicholas Piggin, 2025/05/11