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[Qemu-ppc] [PATCH 2/6] openpic: remove pcsr (CPU sensitivity register)
From: |
Scott Wood |
Subject: |
[Qemu-ppc] [PATCH 2/6] openpic: remove pcsr (CPU sensitivity register) |
Date: |
Thu, 13 Dec 2012 20:12:00 -0600 |
I could not find this register in any spec (FSL, IBM, or OpenPIC)
and the code doesn't do anything with it but initialize, save,
or restore it.
Signed-off-by: Scott Wood <address@hidden>
---
hw/openpic.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/hw/openpic.c b/hw/openpic.c
index 7e72c29..57218f3 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -205,7 +205,6 @@ typedef struct IRQ_src_t {
typedef struct IRQ_dst_t {
uint32_t pctp; /* CPU current task priority */
- uint32_t pcsr; /* CPU sensitivity register */
IRQ_queue_t raised;
IRQ_queue_t servicing;
qemu_irq *irqs;
@@ -447,7 +446,6 @@ static void openpic_reset(DeviceState *d)
/* Initialise IRQ destinations */
for (i = 0; i < MAX_CPU; i++) {
opp->dst[i].pctp = 15;
- opp->dst[i].pcsr = 0x00000000;
memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
opp->dst[i].raised.next = -1;
memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
@@ -1072,7 +1070,6 @@ static void openpic_save(QEMUFile* f, void *opaque)
for (i = 0; i < opp->nb_cpus; i++) {
qemu_put_be32s(f, &opp->dst[i].pctp);
- qemu_put_be32s(f, &opp->dst[i].pcsr);
openpic_save_IRQ_queue(f, &opp->dst[i].raised);
openpic_save_IRQ_queue(f, &opp->dst[i].servicing);
}
@@ -1119,7 +1116,6 @@ static int openpic_load(QEMUFile* f, void *opaque, int
version_id)
for (i = 0; i < opp->nb_cpus; i++) {
qemu_get_be32s(f, &opp->dst[i].pctp);
- qemu_get_be32s(f, &opp->dst[i].pcsr);
openpic_load_IRQ_queue(f, &opp->dst[i].raised);
openpic_load_IRQ_queue(f, &opp->dst[i].servicing);
}
--
1.7.9.5
- [Qemu-ppc] [PATCH 0/6] openpic: first batch of cleanups and minor fixes, Scott Wood, 2012/12/13
- [Qemu-ppc] [PATCH 1/6] openpic: symbolicize some magic numbers, Scott Wood, 2012/12/13
- [Qemu-ppc] [PATCH 4/6] openpic: don't crash on a register access without a CPU context, Scott Wood, 2012/12/13
- [Qemu-ppc] [PATCH 5/6] openpic: BRR1 is not a CPU-specific register., Scott Wood, 2012/12/13
- [Qemu-ppc] [PATCH 2/6] openpic: remove pcsr (CPU sensitivity register),
Scott Wood <=
- [Qemu-ppc] [PATCH 6/6] openpic: s/opp->nb_irqs -1/opp->nb_cpus - 1/, Scott Wood, 2012/12/13
- [Qemu-ppc] [PATCH 3/6] openpic: support large vectors on FSL mpic, Scott Wood, 2012/12/13
- Re: [Qemu-ppc] [PATCH 0/6] openpic: first batch of cleanups and minor fixes, Alexander Graf, 2012/12/14