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[Qemu-ppc] [PULL 074/118] spapr: Add ibm, chip-id property in device tre
From: |
Alexander Graf |
Subject: |
[Qemu-ppc] [PULL 074/118] spapr: Add ibm, chip-id property in device tree |
Date: |
Wed, 4 Jun 2014 14:44:15 +0200 |
From: Alexey Kardashevskiy <address@hidden>
This adds a "ibm,chip-id" property for CPU nodes which should be the same
for all cores in the same CPU socket. The recent guest kernels use this
information to associate threads with sockets.
Refer to the kernel commit 256f2d4b463d3030ebc8d2b54f427543814a2bdc
for more details.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
hw/ppc/spapr.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index fba8686..877e1f0 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -313,6 +313,9 @@ static void *spapr_create_fdt_skel(hwaddr initrd_base,
uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
int i, smt = kvmppc_smt_threads();
unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
+ QemuOpts *opts = qemu_opts_find(qemu_find_opts("smp-opts"), NULL);
+ unsigned sockets = opts ? qemu_opt_get_number(opts, "sockets", 0) : 0;
+ uint32_t cpus_per_socket = sockets ? (smp_cpus / sockets) : 1;
fdt = g_malloc0(FDT_MAX_SIZE);
_FDT((fdt_create(fdt, FDT_MAX_SIZE)));
@@ -470,6 +473,9 @@ static void *spapr_create_fdt_skel(hwaddr initrd_base,
page_sizes_prop, page_sizes_prop_size)));
}
+ _FDT((fdt_property_cell(fdt, "ibm,chip-id",
+ cs->cpu_index / cpus_per_socket)));
+
_FDT((fdt_end_node(fdt)));
}
--
1.8.1.4
- [Qemu-ppc] [PULL 054/118] util: Add AES ShiftRows and InvShiftRows Tables, (continued)
- [Qemu-ppc] [PULL 054/118] util: Add AES ShiftRows and InvShiftRows Tables, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 056/118] target-i386: Use Common ShiftRows and InvShiftRows Tables, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 052/118] spapr_pci: fix MSI limit, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 053/118] util: Add S-Box and InvS-Box Arrays to Common AES Utils, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 048/118] target-ppc: Introduce DFP Encode BCD to DPD, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 071/118] PPC: Add u-boot firmware for e500, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 015/118] libdecnumber: Introduce libdecnumber Code, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 057/118] target-arm: Use Common Tables in AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 059/118] KVM: PPC: Don't secretly add 1T segment feature to CPU, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 066/118] PPC: Fix SPR access control of L1CFG0, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 074/118] spapr: Add ibm, chip-id property in device tree,
Alexander Graf <=
- [Qemu-ppc] [PULL 073/118] spapr: Add support for time base offset migration, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 027/118] target-ppc: Introduce Generator Macros for DFP Arithmetic Forms, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 061/118] PPC: e500: implement PCI INTx routing, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 064/118] PPC: Make all e500 CPUs SVR aware, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 050/118] target-ppc: Introduce DFP Insert Biased Exponent, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 058/118] target-ppc: Refactor AES Instructions, Alexander Graf, 2014/06/04
- [Qemu-ppc] [PULL 075/118] macio: handle non-block ATAPI DMA transfers, Alexander Graf, 2014/06/04