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Re: [PATCH 16/33] target/ppc: Implement Vector Insert Word from GPR usin
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From: |
Paul A. Clarke |
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Subject: |
Re: [PATCH 16/33] target/ppc: Implement Vector Insert Word from GPR using Immediate insns |
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Date: |
Tue, 26 Oct 2021 13:45:26 -0500 |
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User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Tue, Oct 26, 2021 at 09:58:15AM -0700, Richard Henderson wrote:
> On 10/26/21 7:33 AM, Matheus K. Ferst wrote:
> > It says that "if UIM is greater than N, the result is undefined." My
> > first read was also that the outcome is "boundedly undefined," but I
> > guess it can be understood as "the resulting value in VRT will be
> > undefined" (like when the pseudo-code uses "VRT <- 0xUUUU_..._UUUU"), in
> > which case this patch and Mambo are correct.
>
> If the reference simulator is fine with it, I am too.
FYI, it appears that the hardware does a partial insert, per an experiment:
```
1: x/i $pc
=> 0x100006d4 <foo+4>: vinsw v2,r3,14
(gdb) p $v2.v4_int32
$1 = {0x1, 0x1, 0x1, 0x1}
(gdb) p $r3
$2 = 0x12345678
(gdb) nexti
(gdb) p $v2.v4_int32
$3 = {0x1234, 0x1, 0x1, 0x1}
````
> I'm just a bit disappointed with the laxness of the pseudocode -- they've
> got that 0xuuuu syntax elsewhere, but not here.
PC
[PATCH 16/33] target/ppc: Implement Vector Insert Word from GPR using Immediate insns, matheus . ferst, 2021/10/21
[PATCH 17/33] target/ppc: Implement Vector Insert from VSR using GPR index insns, matheus . ferst, 2021/10/21
[PATCH 19/33] target/ppc: Implement Vector Extract Double to VSR using GPR index insns, matheus . ferst, 2021/10/21
[PATCH 20/33] target/ppc: Introduce REQUIRE_VSX macro, matheus . ferst, 2021/10/21
[PATCH 21/33] target/ppc: moved stxv and lxv from legacy to decodtree, matheus . ferst, 2021/10/21