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[Qemu-riscv] [PULL 32/34] hw/riscv: Extend the kernel loading support
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 32/34] hw/riscv: Extend the kernel loading support |
Date: |
Thu, 27 Jun 2019 08:20:09 -0700 |
From: Alistair Francis <address@hidden>
Extend the RISC-V kernel loader to support Image and uImage files.
A Linux kernel can now be booted with:
qemu-system-riscv64 -machine virt -bios fw_jump.bin -kernel Image
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Bin Meng <address@hidden>
Tested-by: Bin Meng <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/boot.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 883df49a0c65..ff023f42d01d 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -56,12 +56,22 @@ target_ulong riscv_load_kernel(const char *kernel_filename)
uint64_t kernel_entry, kernel_high;
if (load_elf(kernel_filename, NULL, NULL, NULL,
- &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0) < 0) {
- error_report("could not load kernel '%s'", kernel_filename);
- exit(1);
+ &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0) > 0) {
+ return kernel_entry;
}
- return kernel_entry;
+ if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL,
+ NULL, NULL, NULL) > 0) {
+ return kernel_entry;
+ }
+
+ if (load_image_targphys_as(kernel_filename, KERNEL_BOOT_ADDRESS,
+ ram_size, NULL) > 0) {
+ return KERNEL_BOOT_ADDRESS;
+ }
+
+ error_report("could not load kernel '%s'", kernel_filename);
+ exit(1);
}
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
--
2.21.0
- [Qemu-riscv] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware, (continued)
- [Qemu-riscv] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 33/34] roms: Add OpenSBI version 0.3, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 28/34] riscv: sifive_u: Do not create hard-coded phandles in DT, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 32/34] hw/riscv: Extend the kernel loading support,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 24/34] RISC-V: Update syscall list for 32-bit support., Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 30/34] hw/riscv: Split out the boot functions, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 25/34] riscv: virt: Add cpu-topology DT node., Palmer Dabbelt, 2019/06/27