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[Qemu-riscv] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding |
Date: |
Thu, 27 Jun 2019 08:19:48 -0700 |
From: Bin Meng <address@hidden>
The largest pci bus number should be calculated from ECAM size,
instead of its base address.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 84d94d0c42d8..487f61404b21 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -298,7 +298,7 @@ static void *create_fdt(RISCVVirtState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
- memmap[VIRT_PCIE_ECAM].base /
+ memmap[VIRT_PCIE_ECAM].size /
PCIE_MMCFG_SIZE_MIN - 1);
qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
qemu_fdt_setprop_cells(fdt, nodename, "reg", 0,
memmap[VIRT_PCIE_ECAM].base,
--
2.21.0
- [Qemu-riscv] [PULL 15/34] target/riscv: Add the mcountinhibit CSR, (continued)
- [Qemu-riscv] [PULL 15/34] target/riscv: Add the mcountinhibit CSR, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 06/34] RISC-V: Raise access fault exceptions on PMP violations, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 18/34] target/riscv: Require either I or E base extension, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 33/34] roms: Add OpenSBI version 0.3, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 28/34] riscv: sifive_u: Do not create hard-coded phandles in DT, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 32/34] hw/riscv: Extend the kernel loading support, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 24/34] RISC-V: Update syscall list for 32-bit support., Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 30/34] hw/riscv: Split out the boot functions, Palmer Dabbelt, 2019/06/27