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[Qemu-riscv] [PULL 18/34] target/riscv: Require either I or E base exten
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 18/34] target/riscv: Require either I or E base extension |
Date: |
Thu, 27 Jun 2019 08:19:55 -0700 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ba1325f43533..1689ffecf85f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -373,6 +373,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+ if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
+ error_setg(errp,
+ "Either I or E extension must be set");
+ return;
+ }
+
if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
cpu->cfg.ext_a & cpu->cfg.ext_f &
cpu->cfg.ext_d)) {
--
2.21.0
- [Qemu-riscv] [PULL 21/34] RISC-V: Add support for the Zifencei extension, (continued)
- [Qemu-riscv] [PULL 21/34] RISC-V: Add support for the Zifencei extension, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 31/34] hw/riscv: Add support for loading a firmware, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 13/34] target/riscv: Restructure deprecatd CPUs, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 07/34] RISC-V: Check for the effective memory privilege mode during PMP checks, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 20/34] target/riscv: Add support for disabling/enabling Counters, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 22/34] RISC-V: Add support for the Zicsr extension, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 15/34] target/riscv: Add the mcountinhibit CSR, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 06/34] RISC-V: Raise access fault exceptions on PMP violations, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 18/34] target/riscv: Require either I or E base extension,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 33/34] roms: Add OpenSBI version 0.3, Palmer Dabbelt, 2019/06/27