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[Qemu-riscv] [PULL 14/34] target/riscv: Add the privledge spec version 1
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0 |
Date: |
Thu, 27 Jun 2019 08:19:51 -0700 |
From: Alistair Francis <address@hidden>
Add support for the ratified RISC-V privledge spec.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.h | 1 +
target/riscv/insn_trans/trans_privileged.inc.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5eb9cab2ad62..d559d28bcda8 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -81,6 +81,7 @@ enum {
#define USER_VERSION_2_02_0 0x00020200
#define PRIV_VERSION_1_09_1 0x00010901
#define PRIV_VERSION_1_10_0 0x00011000
+#define PRIV_VERSION_1_11_0 0x00011100
#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c
b/target/riscv/insn_trans/trans_privileged.inc.c
index 664d6ba3f2cc..c5e4b3e49a3e 100644
--- a/target/riscv/insn_trans/trans_privileged.inc.c
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -90,7 +90,7 @@ static bool trans_wfi(DisasContext *ctx, arg_wfi *a)
static bool trans_sfence_vma(DisasContext *ctx, arg_sfence_vma *a)
{
#ifndef CONFIG_USER_ONLY
- if (ctx->priv_ver == PRIV_VERSION_1_10_0) {
+ if (ctx->priv_ver >= PRIV_VERSION_1_10_0) {
gen_helper_tlb_flush(cpu_env);
return true;
}
--
2.21.0
- [Qemu-riscv] [PULL 31/34] hw/riscv: Add support for loading a firmware, (continued)
- [Qemu-riscv] [PULL 31/34] hw/riscv: Add support for loading a firmware, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 13/34] target/riscv: Restructure deprecatd CPUs, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 07/34] RISC-V: Check for the effective memory privilege mode during PMP checks, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 20/34] target/riscv: Add support for disabling/enabling Counters, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 22/34] RISC-V: Add support for the Zicsr extension, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 15/34] target/riscv: Add the mcountinhibit CSR, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 06/34] RISC-V: Raise access fault exceptions on PMP violations, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 18/34] target/riscv: Require either I or E base extension, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/06/27
- [Qemu-riscv] [PULL 33/34] roms: Add OpenSBI version 0.3, Palmer Dabbelt, 2019/06/27