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[PULL 01/38] target/riscv: Convert MIP CSR to target_ulong
From: |
Palmer Dabbelt |
Subject: |
[PULL 01/38] target/riscv: Convert MIP CSR to target_ulong |
Date: |
Mon, 2 Mar 2020 16:48:11 -0800 |
From: Alistair Francis <address@hidden>
The MIP CSR is a xlen CSR, it was only 32-bits to allow atomic access.
Now that we don't use atomics for MIP we can change this back to a xlen
CSR.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8c86ebc109..efbd676edb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -224,7 +224,7 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int
flags)
#ifndef CONFIG_USER_ONLY
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
- qemu_fprintf(f, " %s 0x%x\n", "mip ", env->mip);
+ qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index de0a8d893a..95de9e58a2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -121,7 +121,7 @@ struct CPURISCVState {
target_ulong mhartid;
target_ulong mstatus;
- uint32_t mip;
+ target_ulong mip;
uint32_t miclaim;
target_ulong mie;
--
2.25.0.265.gbab2e86ba0-goog
- [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3, Palmer Dabbelt, 2020/03/02
- [PULL 02/38] target/riscv: Add the Hypervisor extension, Palmer Dabbelt, 2020/03/02
- [PULL 01/38] target/riscv: Convert MIP CSR to target_ulong,
Palmer Dabbelt <=
- [PULL 05/38] target/riscv: Rename the H irqs to VS irqs, Palmer Dabbelt, 2020/03/02
- [PULL 03/38] target/riscv: Add the Hypervisor CSRs to CPUState, Palmer Dabbelt, 2020/03/02
- [PULL 08/38] target/riscv: Fix CSR perm checking for HS mode, Palmer Dabbelt, 2020/03/02
- [PULL 11/38] target/riscv: Add Hypervisor CSR access functions, Palmer Dabbelt, 2020/03/02
- [PULL 09/38] target/riscv: Print priv and virt in disas log, Palmer Dabbelt, 2020/03/02
- [PULL 06/38] target/riscv: Add the virtulisation mode, Palmer Dabbelt, 2020/03/02
- [PULL 07/38] target/riscv: Add the force HS exception mode, Palmer Dabbelt, 2020/03/02
- [PULL 14/38] target/riscv: Add virtual register swapping function, Palmer Dabbelt, 2020/03/02
- [PULL 17/38] target/riscv: Extend the SIP CSR to support virtulisation, Palmer Dabbelt, 2020/03/02
- [PULL 21/38] target/riscv: Add hypvervisor trap support, Palmer Dabbelt, 2020/03/02