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[PULL 08/38] target/riscv: Fix CSR perm checking for HS mode
From: |
Palmer Dabbelt |
Subject: |
[PULL 08/38] target/riscv: Fix CSR perm checking for HS mode |
Date: |
Mon, 2 Mar 2020 16:48:18 -0800 |
From: Alistair Francis <address@hidden>
Update the CSR permission checking to work correctly when we are in
HS-mode.
Signed-off-by: Alistair Francis <address@hidden>
Reviewed-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/csr.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index ca27359c7e..c63b2f980c 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -801,12 +801,22 @@ int riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value,
/* check privileges and return -1 if check fails */
#if !defined(CONFIG_USER_ONLY)
- int csr_priv = get_field(csrno, 0x300);
+ int effective_priv = env->priv;
int read_only = get_field(csrno, 0xC00) == 3;
- if ((!env->debugger) && (env->priv < csr_priv)) {
- return -1;
+
+ if (riscv_has_ext(env, RVH) &&
+ env->priv == PRV_S &&
+ !riscv_cpu_virt_enabled(env)) {
+ /*
+ * We are in S mode without virtualisation, therefore we are in HS
Mode.
+ * Add 1 to the effective privledge level to allow us to access the
+ * Hypervisor CSRs.
+ */
+ effective_priv++;
}
- if (write_mask && read_only) {
+
+ if ((write_mask && read_only) ||
+ (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
return -1;
}
#endif
--
2.25.0.265.gbab2e86ba0-goog
- [PULL] RISC-V Patches for the 5.0 Soft Freeze, Part 3, Palmer Dabbelt, 2020/03/02
- [PULL 02/38] target/riscv: Add the Hypervisor extension, Palmer Dabbelt, 2020/03/02
- [PULL 01/38] target/riscv: Convert MIP CSR to target_ulong, Palmer Dabbelt, 2020/03/02
- [PULL 05/38] target/riscv: Rename the H irqs to VS irqs, Palmer Dabbelt, 2020/03/02
- [PULL 03/38] target/riscv: Add the Hypervisor CSRs to CPUState, Palmer Dabbelt, 2020/03/02
- [PULL 08/38] target/riscv: Fix CSR perm checking for HS mode,
Palmer Dabbelt <=
- [PULL 11/38] target/riscv: Add Hypervisor CSR access functions, Palmer Dabbelt, 2020/03/02
- [PULL 09/38] target/riscv: Print priv and virt in disas log, Palmer Dabbelt, 2020/03/02
- [PULL 06/38] target/riscv: Add the virtulisation mode, Palmer Dabbelt, 2020/03/02
- [PULL 07/38] target/riscv: Add the force HS exception mode, Palmer Dabbelt, 2020/03/02
- [PULL 14/38] target/riscv: Add virtual register swapping function, Palmer Dabbelt, 2020/03/02
- [PULL 17/38] target/riscv: Extend the SIP CSR to support virtulisation, Palmer Dabbelt, 2020/03/02
- [PULL 21/38] target/riscv: Add hypvervisor trap support, Palmer Dabbelt, 2020/03/02
- [PULL 04/38] target/riscv: Add support for the new execption numbers, Palmer Dabbelt, 2020/03/02